Experiences with the Sparse Matrix-Vector Multiplication on a Many-core Processor

被引：1

作者：

Pichel, Juan C. ^{[1
]}

Rivera, Francisco F. ^{[1
]}

机构：

[1] Univ Santiago de Compostela, Ctr Invest Tecnol Informac CITIUS, Santiago De Compostela, Spain

来源：

2012 IEEE 26TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS & PHD FORUM (IPDPSW) | 2012年

关键词：

many-core; sparse matrix; performance; power efficiency;

D O I：

10.1109/IPDPSW.2012.17

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Industry is moving towards many-core processors, which are expected to consist of tens or even hundreds of cores. One of these future processors is the 48-core experimental processor Single-Chip Cloud Computer (SCC). The SCC was created by Intel Labs as a platform for many-core research. The characteristics of this system turns it into a big challenge for researchers in order to extract performance from such complex architecture. In this work we study and explore the behavior of an irregular application such as the Sparse Matrix-Vector multiplication (SpMV) on the SCC processor. An evaluation in terms of performance and power efficiency is provided. Our experiments give some key insights that can serve as guidelines for the understanding and optimization of the SpMV kernel on this architecture. Furthermore, a comparison of the SCC processor with several leading multicore processors and GPUs is performed.

引用

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页码：7 / 15

页数：9

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