Transient and Static Hybrid-Triggered Active Clamp Design for Power-Rail ESD Protection

被引:18
|
作者
Lu, Guangyi [1 ]
Wang, Yuan [1 ]
Zhang, Xing [1 ]
机构
[1] Peking Univ, Inst Microelect, Key Lab Microelect Device & Circuits, Beijing 100871, Peoples R China
关键词
Electrostatic discharge (ESD); static clamp; transient clamp; transmission line pulsing (TLP) test; CIRCUITS;
D O I
10.1109/TED.2016.2618344
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A transient and static hybrid-triggered active clamp is proposed in this paper. By skillfully incorporating different detection mechanisms, the proposed clamp achieves enhanced static electrical overstress protection capability over the transient one. Furthermore, the proposed clamp achieves improved electrostatic discharge reaction speed in both human body model and charged device model events over the static one. Moreover, the superior transient-noise immunity of the proposed clamp over traditional transient ones is essentially revealed in this paper. The proposed clamp is successfully verified in a 65-nm bulk CMOS process. In addition, the design flexibility of the proposed clamp for other processes is also deeply discussed in this paper.
引用
收藏
页码:4654 / 4660
页数:7
相关论文
共 50 条
  • [21] Design of Power-Rail ESD Clamp Circuit with Adjustable Holding Voltage against Mis-trigger or Transient-Induced Latch-On Events
    Yeh, Chih-Ting
    Liang, Yung-Chih
    Ker, Ming-Dou
    2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 1403 - 1406
  • [22] PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit
    Yeh, Chih-Ting
    Ker, Ming-Dou
    MICROELECTRONICS RELIABILITY, 2013, 53 (02) : 208 - 214
  • [23] Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs
    Chen, Shih-Hung
    Ker, Ming-Dou
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2009, 56 (05) : 359 - 363
  • [24] Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit Against False Trigger During Fast Power-ON Events
    Huang, Han-Sheng
    Ker, Ming-Dou
    2021 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2021,
  • [25] Fully Integrated GaN-on-Silicon Power-Rail ESD Clamp Circuit Without Transient Leakage Current During Normal Power-on Operation
    Wang, Wei-Cheng
    Ker, Ming-Dou
    IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2024, 12 : 760 - 769
  • [26] Area-Efficient Power-Rail ESD Clamp Circuit with SCR Device Embedded into ESD-Transient Detection Circuit in a 65nm CMOS Process
    Yeh, Chih-Ting
    Ker, Ming-Dou
    2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
  • [27] Area-Efficient Power-Rail ESD Clamp Circuit with SCR Device Embedded into ESD-Transient Detection Circuit in a 65nm CMOS Process
    Yeh, Chih-Ting
    Ker, Ming-Dou
    2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
  • [28] Design of Power-Rail ESD Clamp With Dynamic Timing-Voltage Detection Against False Trigger During Fast Power-ON Events
    Chen, Jie-Ting
    Ker, Ming-Dou
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (03) : 838 - 846
  • [29] Power-Rail ESD Clamp Circuit with Polysilicon Diodes Against False Trigger During Fast Power-on Events
    Chen, Jie-Ting
    Ker, Ming-Dou
    2018 40TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD), 2018,
  • [30] A False Trigger-Strengthened and Area-Saving Power-Rail Clamp Circuit with High ESD Performance
    Ma, Boyang
    Chen, Shupeng
    Wang, Shulong
    Qian, Lingli
    Han, Zeen
    Huang, Wei
    Fu, Xiaojun
    Liu, Hongxia
    MICROMACHINES, 2023, 14 (06)