PLL frequency synthesizer with an auxiliary programmable divider

The lock-up time of a PLL frequency synthesizer depends on each loop gain. In this paper, we pay attention to the gain of a programmable divider which is one of the important elements of PLL, and propose a new method for improving the gain of programmable divider. In order to achieve the increase in the gain of the programmable divider, we already proposed a new PLL frequency synthesizer with multi-programmable divider by which the gain is increased even when the same reference frequency and the same division ratio as usual are used. In this paper we propose a simple PLL frequency synthesizer with an auxiliary programmable divider which is suitable for LSI implementation. It will be shown by the theoretical considerations and experimental results that a higher speed lock-up time can be achieved.