Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

被引:78
|
作者
Herrera-Alzu, I. [1 ]
Lopez-Vallejo, M. [1 ]
机构
[1] Univ Politecn Madrid, Dept Elect Engn, ETSI Telecomunicac, E-28040 Madrid, Spain
关键词
Field Programmable Gate Array (FPGA); reconfiguration; scrubbing; single event upset; Xilinx; SINGLE-EVENT; MITIGATION;
D O I
10.1109/TNS.2012.2231881
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
SRAM-based FPGAs are in-field reconfigurable an unlimited number of times. This characteristic, together with their high performance and high logic density, proves to be very convenient for a number of ground and space level applications. One drawback of this technology is that it is susceptible to ionizing radiation, and this sensitivity increases with technology scaling. This is a first order concern for applications in harsh radiation environments, and starts to be a concern for high reliability ground applications. Several techniques exist for coping with radiation effects at user application. In order to be effective they need to be complemented with configuration memory scrubbing, which allows error mitigation and prevents failures due to error accumulation. Depending on the radiation environment and on the system dependability requirements, the configuration scrubber design can become more or less complex. This paper classifies and presents current and novel design methodologies and architectures for SRAM-based FPGAs, and in particular for Xilinx Virtex-4QV/5QV, configuration memory scrubbers.
引用
收藏
页码:376 / 385
页数:10
相关论文
共 50 条
  • [41] DDRII SDRAM Memory Controller Interface Design and Application Based on Virtex-5 FPGA
    Li, Binfei
    Liu, Jun
    Zhou, Fudong
    COMMUNICATIONS, SIGNAL PROCESSING, AND SYSTEMS, 2018, 423 : 909 - 917
  • [42] Testing Faults in SRAM Memory of Virtex-4 FPGA
    Niamat, Mohammed
    Lalla, Manoj
    Kim, Junghwan
    2009 52ND IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 2009, : 965 - 970
  • [43] Design of HDLC Controller Based on Xilinx FPGA
    Lie, Wang
    Ming, Yi
    2011 INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE AND NETWORK TECHNOLOGY (ICCSNT), VOLS 1-4, 2012, : 1362 - 1366
  • [44] PROTECTING INTELLECTUAL PROPERTY IN FPGA XILINX DESIGN
    Cheremisinov, D., I
    PRIKLADNAYA DISKRETNAYA MATEMATIKA, 2014, 24 (02): : 110 - +
  • [46] Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs
    Schuck, Christian
    Haetzer, Bastian
    Becker, Juergen
    INTERNATIONAL JOURNAL OF RECONFIGURABLE COMPUTING, 2011, 2011
  • [47] Design and Analysis of an Efficient Repository System for Protein Coefficients in Systolic Array-Based Architecture by Using Xilinx Virtex-5 FPGA
    Isa, M. N.
    Muhsen, D.
    Ahmad, M. I.
    Murad, S. A. Z.
    Mohyar, S. N.
    Ismail, R. C.
    Benkrid, K.
    ADVANCED SCIENCE LETTERS, 2017, 23 (11) : 11267 - 11271
  • [48] Design and implementation of a novel FIR filter architecture with boundary handling on Xilinx VIRTEX FPGAs
    Benkrid, A
    Benkrid, K
    Crookes, D
    FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, 2003, 2778 : 553 - 564
  • [49] Configuration Memory Scrubbing of the Xilinx Zynq-7000 FPGA using a Mixed 2-D Coding Technique
    Vlagkoulis, Vasileios
    Sari, Aitzan
    Proko, Juljan
    Zografakis, Dimitrios
    Psarakis, Mihalis
    Tavoularis, Antonios
    Furano, Gianluca
    Boatella-Polo, Cesar
    Poivey, Christian
    Ferlet-Cavrois, Veronique
    Kastriotou, Maria
    Martinez, Pablo Fernandez
    Alia, Ruben Garcia
    2019 19TH EUROPEAN CONFERENCE ON RADIATION AND ITS EFFECTS ON COMPONENTS AND SYSTEMS (RADECS), 2022, : 192 - 195
  • [50] Real-Time Data Processing for an Advanced Imaging System Using the Xilinx Virtex-5 FPGA
    Werne, Thomas A.
    Bekker, Dmitriy L.
    Pingree, Paula J.
    2010 IEEE AEROSPACE CONFERENCE PROCEEDINGS, 2010,