A Nanophotonic Interconnect for High-Performance Many-Core Computation

被引：4
|
作者：
Beausoleil, R. G. [1 ]
Fiorentino, M. [1 ]
Ahn, J. [2 ]
Binkert, N. [2 ]
Davis, A. [2 ]
Fattal, D. [1 ]
Jouppi, N. P. [2 ]
McLaren, M. [3 ]
Santori, C. M. [1 ]
Schreiber, R. S. [2 ]
Spillane, S. M. [1 ]
Vantrease, D. [2 ]
Xu, Q. [1 ]
机构：
[1] HP Labs, Informat & Quantum Syst, 1501 Page Mill Rd,MS 1123, Palo Alto, CA 94304 USA
[2] HP Labs, Exascale Comp, Palo Alto, CA 94304 USA
[3] HP Labs, Exascale Comp, Bristol BS34 8QZ, Avon, England
来源：
2008 5TH IEEE INTERNATIONAL CONFERENCE ON GROUP IV PHOTONICS | 2008年
关键词：
D O I：
10.1109/GROUP4.2008.4638201
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We describe the results of a design study of DWDM on-chip and off-chip nanophotonic interconnects and device technologies that could improve computing performance by a factor of 20 above industry projections over the next decade.
引用
收藏
页码：365 / 367
页数：3
相关论文
共 50 条
  • [21] Near-Side Prefetch Throttling: Adaptive Prefetching for High-Performance Many-Core Processors
    Heirman, Wim
    Du Bois, Kristof
    Vandriessche, Yves
    Eyerman, Stijn
    Hur, Ibrahim
    27TH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES (PACT 2018), 2018,
  • [22] Preliminary Approach to Parallelizing Autonomous Driving Applications Using High-Performance Many-core Processor
    He, Xuankeng
    Azumi, Takuya
    2024 IEEE 30TH INTERNATIONAL CONFERENCE ON EMBEDDED AND REAL-TIME COMPUTING SYSTEMS AND APPLICATIONS, RTCSA 2024, 2024, : 134 - 135
  • [23] Scalable High-Performance Parallel Design for Network Intrusion Detection Systems on Many-Core Processors
    Jiang, Haiyang
    Zhang, Guangxing
    Xie, Gaogang
    Salamatian, Kave
    Mathy, Laurent
    2013 ACM/IEEE SYMPOSIUM ON ARCHITECTURES FOR NETWORKING AND COMMUNICATIONS SYSTEMS (ANCS), 2013, : 137 - 146
  • [24] A cylinder computation model for many-core parallel computing
    Zhang, Nan
    Duan, Zhenhua
    Tian, Cong
    THEORETICAL COMPUTER SCIENCE, 2013, 497 : 68 - 83
  • [25] Automated Modeling and Emulation of Interconnect Designs for Many-Core Chip Multiprocessors
    Ihrig, Colin J.
    Melhem, Rami
    Jones, Alex K.
    PROCEEDINGS OF THE 47TH DESIGN AUTOMATION CONFERENCE, 2010, : 431 - 436
  • [26] A Packet-switched Interconnect for Many-core Systems with BE and RT Service
    Ma, Runan
    Hui, Zhida
    Jantsch, Axel
    2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2015, : 980 - 983
  • [27] A Hierarchical Grid Algorithm for Accelerating High-Performance Conjugate Gradient Benchmark on Sunway Many-core Processor
    Liao, Chenzhi
    Chen, Junshi
    Han, Wenting
    Cao, Huanqi
    Su, Zhichao
    Yin, Wanwang
    An, Hong
    PROCEEDINGS OF THE 3RD INTERNATIONAL CONFERENCE ON COMMUNICATION AND INFORMATION PROCESSING (ICCIP 2017), 2017, : 361 - 368
  • [28] High-Performance 3D Compressive Sensing MRI Reconstruction Using Many-Core Architectures
    Kim, Daehyun
    Trzasko, Joshua
    Smelyanskiy, Mikhail
    Haider, Clifton
    Dubey, Pradeep
    Manduca, Armando
    INTERNATIONAL JOURNAL OF BIOMEDICAL IMAGING, 2011, 2011
  • [29] High performance in silico virtual drug screening on many-core processors
    McIntosh-Smith, Simon
    Price, James
    Sessions, Richard B.
    Ibarra, Amaurys A.
    INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS, 2015, 29 (02): : 119 - 134
  • [30] High performance parallelization of Boyer–Moore algorithm on many-core accelerators
    Yosang Jeong
    Myungho Lee
    Dukyun Nam
    Jik-Soo Kim
    Soonwook Hwang
    Cluster Computing, 2015, 18 : 1087 - 1098
12345