VLSI implementation of a Binary Neural Network-two case studies

被引：0

作者：

Bermak, A ^{[1
]}

Austin, J ^{[1
]}

机构：

[1] Edith Cowan Univ, Sch Engn & Mech, Joondalup, WA 6027, Australia

来源：

PROCEEDINGS OF THE SEVENTH INTERNATIONAL CONFERENCE ON MICROELECTRONICS FOR NEURAL, FUZZY AND BIO-INSPIRED SYSTEMS, MICORNEURO'99 | 1999年

关键词：

Binary Neural Networks; VLSI implementation; bit-level architecture; internal storage processors;

D O I：

10.1109/MN.1999.758889

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

A comparison between a bit-level and a conventional VLSI implementation of a binary neural network is presented. This network is based on Correlation Matrix Memory (CMM) that stores relationships between pairs of binary vectors. The tit-level architecture consists of an n x m array of bit-level processors holding the storage and computation elements. The conventional CMM architecture consists of a RAM memory holding the CMM storage and an array of counters., Since we are interested in the VLSI implementation of such networks the hardware complexities and speeds of both bit-level and conventional architecture were compared by using VLSI tools. It is shown that a significant speedup is achieved by using the bit-level architecture since the speed of this last configuration is not limited by the memory addressing delay. Moreover, the bit-level architecture is very simple and reduces the bus/routing, making the architecture suitable for VLSI implementation. The main drawback of such an approach compared to the conventional one is the demand for a high number of adders for dealing with a large number of inputs.

引用

页码：374 / 379

页数：6

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