VLSI implementation of a Binary Neural Network-two case studies

被引：0

作者：

Bermak, A ^{[1
]}

Austin, J ^{[1
]}

机构：

[1] Edith Cowan Univ, Sch Engn & Mech, Joondalup, WA 6027, Australia

来源：

PROCEEDINGS OF THE SEVENTH INTERNATIONAL CONFERENCE ON MICROELECTRONICS FOR NEURAL, FUZZY AND BIO-INSPIRED SYSTEMS, MICORNEURO'99 | 1999年

关键词：

Binary Neural Networks; VLSI implementation; bit-level architecture; internal storage processors;

D O I：

10.1109/MN.1999.758889

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

A comparison between a bit-level and a conventional VLSI implementation of a binary neural network is presented. This network is based on Correlation Matrix Memory (CMM) that stores relationships between pairs of binary vectors. The tit-level architecture consists of an n x m array of bit-level processors holding the storage and computation elements. The conventional CMM architecture consists of a RAM memory holding the CMM storage and an array of counters., Since we are interested in the VLSI implementation of such networks the hardware complexities and speeds of both bit-level and conventional architecture were compared by using VLSI tools. It is shown that a significant speedup is achieved by using the bit-level architecture since the speed of this last configuration is not limited by the memory addressing delay. Moreover, the bit-level architecture is very simple and reduces the bus/routing, making the architecture suitable for VLSI implementation. The main drawback of such an approach compared to the conventional one is the demand for a high number of adders for dealing with a large number of inputs.

引用

页码：374 / 379

页数：6

共 50 条

[1] VLSI implementation of a neural network classifier
Mandisodza, RLK
Luke, DM
Pochec, P
[J]. 1996 CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING - CONFERENCE PROCEEDINGS, VOLS I AND II: THEME - GLIMPSE INTO THE 21ST CENTURY, 1996, : 178 - 181
[2] VLSI implementation of a functional neural network
Panagiotopoulos, DA
Singh, SK
Newcomb, RW
[J]. ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE, 1997, : 701 - 704
[3] VLSI IMPLEMENTATION OF A NEURAL NETWORK MODEL
GRAF, HP
JACKEL, LD
HUBBARD, WE
[J]. COMPUTER, 1988, 21 (03) : 41 - 49
[4] VLSI implementation of an Extended Hamming Neural Network for non-binary pattern recognition
NinodeRivera, L
NakanoMiyatake, M
Sanchez, JC
PerezMeana, H
SanchezSinencio, E
[J]. 38TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2, 1996, : 973 - 977
[5] Pulse coded neural network implementation in VLSI
Shaikh-Husin, N
Po, CW
[J]. IEEE 2000 TENCON PROCEEDINGS, VOLS I-III: INTELLIGENT SYSTEMS AND TECHNOLOGIES FOR THE NEW MILLENNIUM, 2000, : B237 - B241
[6] AN ANALOG VLSI IMPLEMENTATION OF HOPFIELD NEURAL NETWORK
VERLEYSEN, M
JESPERS, PGA
[J]. IEEE MICRO, 1989, 9 (06) : 46 - 55
[7] VLSI implementation of a neural network for auditory processing
Izak, Richard
Zahn, Thomas P.
[J]. Neural Network World, 1998, 8 (06): : 665 - 674
[8] CMOS PWM VLSI implementation of neural network
Chen, L
Shi, BX
[J]. IJCNN 2000: PROCEEDINGS OF THE IEEE-INNS-ENNS INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, VOL III, 2000, : 485 - 488
[9] Compact VLSI implementation of cellular neural network
Paasio, A
Dawidziuk, A
Porra, V
[J]. PROCEEDINGS OF THE 39TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, 1996, : 509 - 512
[10] Asynchronous pulse neural network model for VLSI implementation
Hanagata, M
Horio, Y
Aihara, K
[J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1998, E81A (09) : 1853 - 1859

← 1 2 3 4 5 →