System-on-chip (SoC): Clocking and synchronization issues

被引：1
|
作者：
Sridhar, R [1 ]
机构：
[1] SUNY Buffalo, Dept Comp Sci & Engn, Buffalo, NY 14260 USA
来源：
17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: DESIGN METHODOLOGIES FOR THE GIGASCALE ERA | 2004年
关键词：
D O I：
10.1109/ICVD.2004.1260973
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Technology scaling continues to improve transistor performance and integration to realize complex systems and added functionality in SoC designs. This reduces the energy consumed with a 30% speed improvement per technology generation. The scaling, however comes with some adverse effects posingperceived barriers. In this paper we discuss the design challenges in Ultra Deep Submicron (UDSM) technologies and the scaling problems in SoC circuits for clocking and synchronization. This includes delay variations and functional errors due to various types of noise sources. Correct clocking and synchronization can be achieved through innovative strategies that work at all levels of abstraction.
引用
收藏
页码：520 / 527
页数：8
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