Bitline Separated Gated Multi-Bit (BS-GMB) SONOS for High Density Flash Memory

被引：0
|
作者：
Shim, Won Bo [1 ]
Kim, Seunghyun [1 ]
Kim, Yoon [1 ]
Park, Se Hwan [1 ]
Kim, Sungjun [1 ]
Park, Euyhwan [1 ]
Park, Byung-Gook [1 ]
机构：
[1] Seoul Natl Univ, ISRC, Seoul 151742, South Korea
来源：
2012 12TH IEEE CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO) | 2012年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A novel bitline separated gated multi-bit (BS-GMB) SONOS memory for high density flash memory is newly introduced. Bitline separation method can decrease the number of gate contacts, and simplify the gate contact interconnection. 2N memory nodes with single crystalline silicon channel can be realized in 8F(2) size with this structure.
引用
收藏
页数：4
相关论文
共 38 条
  • [21] Bit cost scalable technology with punch and plug process for ultra high density flash memory
    Tanaka, H.
    Kido, M.
    Yahashi, K.
    Oomura, M.
    Katsumata, R.
    Kito, M.
    Fukuzumi, Y.
    Sato, M.
    Nagata, Y.
    Matsuoka, Y.
    Iwata, Y.
    Aochi, H.
    Nitayama, A.
    2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, : 14 - +
  • [22] Novel multi-bit non-uniform channel charge trapping memory device with virtual-source NAND flash array
    Gu Haiming
    Pan Liyang
    Zhu Peng
    Wu Dong
    Zhang Zhigang
    Xu Jun
    JOURNAL OF SEMICONDUCTORS, 2010, 31 (10)
  • [23] Monolithic 3D Integration of High Endurance Multi-Bit Ferroelectric FET for Accelerating Compute-In-Memory
    Dutta, S.
    Ye, H.
    Chakraborty, W.
    Luo, Y-C
    San Jose, M.
    Grisafe, B.
    Khanna, A.
    Lightcap, I
    Shinde, S.
    Yu, S.
    Datta, S.
    2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2020,
  • [24] High performance multi-bit nonvolatile HfO2 nanocrystal memory using spinodal phase separation of hafnium silicate
    Lin, YH
    Chien, CH
    Lin, CT
    Chen, CW
    Chang, CY
    Lei, TF
    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, : 1080 - 1082
  • [25] Substrate-Bias Assisted Hot Electron Injection Method for High-Speed, Low-Voltage, and Multi-Bit Flash Memories
    An, Ho-Myoung
    Kim, Hee-Dong
    Zhang, Yongjie
    Seo, Yu Jeong
    Kim, Tae Geun
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2011, 50 (12)
  • [26] A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM
    Zhu, Haonan
    Wu, Bi
    Yu, Tianyang
    Chen, Ke
    Yan, Chenggang
    Liu, Weiqiang
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2024, 71 (07) : 3165 - 3178
  • [27] Substrate-bias assisted hot electron injection method for high-speed, low-voltage, and multi-bit flash memories
    School of Electrical Engineering, Korea University, Seoul 136-713, Korea, Republic of
    Jpn. J. Appl. Phys., 12
  • [28] High Speed Frequency-Mapping-Based Associative Memory Using Compact Multi-Bit Encoders and a Path-Selecting Scheme
    Sasaki, Seiryu
    Yasuda, Masahiro
    Kawabata, Akio
    Koide, Tetsushi
    Mattausch, Hans Juergen
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2012, 51 (04)
  • [29] A Low-Cost Improved Method of Raw Bit Error Rate Estimation for NAND Flash Memory of High Storage Density
    Ma, Kainan
    Liu, Ming
    Li, Tao
    Yin, Yibo
    Chen, Hongda
    ELECTRONICS, 2020, 9 (11) : 1 - 14
  • [30] Optimal integration and characteristics of vertical array devices for ultra-high density, Bit-Cost Scalable flash memory
    Fukuzumi, Yoshiaki
    Katsumata, Ryota
    Kito, Masaru
    Kido, Masaru
    Sato, Mitsuru
    Tanaka, Hiroyasu
    Nagata, Yuzo
    Matsuoka, Yasuyuki
    Iwata, Yoshihisa
    Aochi, Hideaki
    Nitayama, Akihiro
    2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, : 449 - +
1234