I/O impedance matching algorithm for high-performance ASICs

被引：8
|
作者：
Zuchowski, PS
Panner, JH
Stout, DW
Adams, JM
Chan, F
Dunn, PE
Huber, AD
Oler, JJ
机构：
来源：
TENTH ANNUAL IEEE INTERNATIONAL ASIC CONFERENCE AND EXHIBIT, PROCEEDINGS | 1997年
关键词：
D O I：
10.1109/ASIC.1997.617019
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper discusses a design style that utilizes an area array of flip-chip solder bump connections, I/O circuit designs that implement a programmable impedance matching algorithm, and a design system that must utilize these features during chip layout, chip checking, and release to manufacturing. Results from a recent test chip will also be given.
引用
收藏
页码：270 / 273
页数：4
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