High Performance CMOS Circuit Design

被引:1
|
作者
Swami, Neelam [1 ]
Khatri, Bhupen [2 ]
机构
[1] Bikaner Tech Univ, Dept Elect & Commun, Bikaner, India
[2] BSNL, JTO Transmiss, New Delhi, India
关键词
D O I
10.1063/5.0002200
中图分类号
O59 [应用物理学];
学科分类号
摘要
The global performance of the systems is always determined by timing elements such as flip-flops and latches, thus the improvement of flip-flops is one of the most critical tasks to enhance the system performance. A careful design of storage elements will contribute in the increased performance and reduce power consumption of a VLSI system. These are extremely important circuit elements in any synchronous VLSI chip. They are not only responsible for correct timing, functionality, and performance of the chips, but also their clocked devices consume a significant portion of the total active power. With increasing requirement for high-performance and low power, flip-flops with fewer transistors are preferred for their low power consumption and small area occupation.
引用
收藏
页数:6
相关论文
共 50 条
  • [1] High performance CMOS static logic circuit design
    Kuo, KC
    Carlson, BS
    [J]. PROCEEDINGS OF THE 44TH IEEE 2001 MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 2001, : 598 - 601
  • [2] Design of high performance CMOS linear readout integrated circuit
    Gao, J
    Lu, WG
    Liu, J
    Cui, WT
    Tang, J
    Chen, ZJ
    Ji, LJ
    [J]. 2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 607 - 610
  • [3] A high performance CMOS band-gap reference circuit design
    Xu, WD
    Xu, DL
    French, I
    [J]. Proceedings of 2005 IEEE International Workshop on VLSI Design and Video Technology, 2005, : 32 - 35
  • [4] RADIATION-TOLERANT HIGH-PERFORMANCE CMOS VLSI CIRCUIT-DESIGN
    HATANO, H
    DOI, K
    [J]. IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1985, 32 (06) : 4031 - 4035
  • [5] High Performance Multistage CMOS Charge Pump Circuit
    Anupama
    Kumar, Anand
    [J]. 2015 4TH INTERNATIONAL CONFERENCE ON RELIABILITY, INFOCOM TECHNOLOGIES AND OPTIMIZATION (ICRITO) (TRENDS AND FUTURE DIRECTIONS), 2015,
  • [6] Design of high performance CMOS current-mode winner-take-all circuit
    Yu, CC
    Tang, YC
    Liu, BD
    [J]. 2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 568 - 572
  • [7] High-speed CMOS Track/Hold circuit design
    Kobayashi, H
    Zin, MAM
    Kobayashi, K
    San, H
    Sato, H
    Ichimura, JI
    Onaya, Y
    Kurosawa, N
    Kimura, Y
    Yuminaka, Y
    Tanaka, K
    Myono, T
    Abe, F
    [J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2001, 27 (1-2) : 161 - 170
  • [8] High-Speed CMOS Track/Hold Circuit Design
    Haruo Kobayashi
    Mohd Asmawi Mohamed Zin
    Kazuya Kobayashi
    Hao San
    Hiroyuki Sato
    Jun-Ichi Ichimura
    Yoshitaka Onaya
    Yuuichi Takahashi
    Naoki Kurosawa
    Yasuyuki Kimura
    Yasushi Yuminaka
    Kouji Tanaka
    Takao Myono
    Fuminori Abe
    [J]. Analog Integrated Circuits and Signal Processing, 2001, 27 : 161 - 170
  • [9] A high performance CMOS voltage reference in one simple circuit
    Chen, Qibin
    Xie, Jin
    Qiu, Hangfang
    Li, Jinghu
    Luo, Zhicong
    [J]. AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2024, 173
  • [10] CMOS High-Performance UWB Active Inductor Circuit
    Momen, H. G.
    Yazgi, M.
    Kopru, R.
    Saatlo, A. N.
    [J]. 2016 12TH CONFERENCE ON PH.D. RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIME), 2016,