A sub-μW Bio-potential Front End in 65nm CMOS

被引:0
|
作者
Kifle, Yonatan [1 ]
Saleh, Hani [1 ]
Mohammad, Baker [1 ]
Ismail, Mohammed [1 ]
机构
[1] Khalifa Univ Sci & Technol, KSRC, Abu Dhabi, U Arab Emirates
关键词
Analog front end; bio-potential amplifier and chopper stabilized amplifier;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A bio-potential amplifier intended for continuous monitoring of vitals characterized by its long operational lifetime is required to operate at the lowest power budget possible. Moreover, a compact active area directly related to portability is essential. This paper presents a 0.55 mu W auto gain controlled bio-potential amplifier implemented in 65nm 1P7M CMOS for ECG signal classifier SoC. A chopper-stabilized amplifier is designed at 0.6V supply voltage to mitigate the DC offset and near DC flicker noise. The input ECG signal level is further set by the four gain levels of the variable gain amplifier (VGA) to provide maximum swing to the ADC. The whole system is integrated into a core are of 0.10mm(2) and can operate at a wide range of 0.6-1.2V supply voltage.
引用
收藏
页码:60 / 63
页数:4
相关论文
共 50 条
  • [1] A 65nm CMOS Current-Mode Receiver Front-End
    Rodriguez, S.
    Rusu, A.
    2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 530 - 533
  • [2] A 90nm CMOS Bio-Potential Signal Readout Front-End with Improved Powerline Interference Rejection
    Ma, Chon-Teng
    Mak, Pui-In
    Vai, Mang-, I
    Mak, Peng-Un
    Pun, Si-Hang
    Feng, Wan
    Martins, R. P.
    ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, : 665 - +
  • [3] A 39 GHz T/R Front-End Module in 65nm CMOS
    Zhang, Xuexue
    Qiao, Kun
    Chen, Qin
    Liang, Yue
    Li, Lianming
    Feng, Jun
    2021 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT), 2021,
  • [4] High Performance Circuit Techniques for Nueral Front-End design in 65nm CMOS
    Nagulapalli, R.
    Hayatleh, K.
    Barker, S.
    Zourob, S.
    Yassine, N.
    Reddy, B. Naresh Kumar
    2018 9TH INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION AND NETWORKING TECHNOLOGIES (ICCCNT), 2018,
  • [5] A VGA Linearity Improvement Technique for ECG Analog Front-End in 65nm CMOS
    Nagulapalli, Rajasekhar
    Hayatleh, Khaled
    Barker, Steve
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2020, 29 (07)
  • [6] A 20μW Dual-Channel Analog Front-End in 65nm CMOS for Portable ECG Monitoring System
    Li, Shuo
    Qi, Nan
    Behravan, Vahid
    Hong, Zhiliang
    Chiang, Patrick Y.
    PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2015,
  • [7] 1.2 GS/s Hadamard Transform Front-End For Compressive Sensing in 65nm CMOS
    Khan, Osama U.
    Wentzloff, David D.
    2013 IEEE RADIO AND WIRELESS SYMPOSIUM (RWS), 2013, : 181 - 183
  • [8] A wideband W-band receiver front-end in 65-nm CMOS
    Khanpour, Mehdi
    Tang, Keith W.
    Garcia, Patrice
    Voinigescu, Sorin P.
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (08) : 1717 - 1730
  • [9] A Passive W-Band Imager in 65nm Bulk CMOS
    Tomkins, A.
    Garcia, P.
    Voinigescu, S. P.
    2009 ANNUAL IEEE COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT SYMPOSIUM - 2009 IEEE CSIC SYMPOSIUM, TECHNICAL DIGEST 2009, 2009, : 91 - +
  • [10] Bluetooth Low Energy (BLE) Direct Down Conversion Receiver Front End in 65nm CMOS Technology
    Nasrollahpour, M.
    Sreekumar, R.
    Hajilou, F.
    Aldacher, M.
    Hamedi-Hagh, S.
    2017 FIRST NEW GENERATION OF CAS (NGCAS), 2017, : 141 - 144