High throughput 2D DCT/IDCT processor for video coding

被引：0

作者：

Ruiz, GA ^{[1
]}

Michell, JA ^{[1
]}

Burón, AM ^{[1
]}

机构：

[1] Univ Cantabria, Dept Elect & Comp, Santander, Spain

来源：

2005 INTERNATIONAL CONFERENCE ON IMAGE PROCESSING (ICIP), VOLS 1-5 | 2005年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper describes the architecture of an 8x8 2-D DCT/IDCT processor with high throughput, reduced hardware, and a parallel-pipeline scheme. This architecture allows the processing elements and arithmetic units to work in parallel at half the frequency of the data input rate. A fully pipelined row-column decomposition method based on two 1-D DCTs and a transpose buffer based on D-type flip-flops are used. The processor has been implemented in a 0.35-mu m CMOS process with a core area of 3mm(2) and 11.7k gates. It meets the requirements of IEEE Std. 1180-1990. The data input rate frequency is 300MHz with a latency of 172 cycles for 2-D DCT and 178 cycles for 2-D IDCT. The proposed design is compact and suitable for HDTV applications.

引用

页码：3521 / 3524

页数：4

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