Ultra high speed Full Adders

被引：12
|
作者：
Navia, K. [1 ]
Mirzaee, R. Faghih [2 ,3 ]
Moaiyeri, M. H. [2 ,3 ]
Nezhad, B. Mazloom [1 ]
Hashemipour, O. [1 ]
Shams, K. [1 ]
机构：
[1] Shahid Beheshti Univ, Fac Elect & Comp Engn, Tehran, Iran
[2] Shahid Beheshti Univ, Microelect Lab, Tehran, Iran
[3] IAU, Tehran, Iran
来源：
IEICE ELECTRONICS EXPRESS | 2008年 / 5卷 / 18期
关键词：
Full Adder cell; high speed; low voltage; Majority function;
D O I：
10.1587/elex.5.744
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Two novel 1-bit Full Adder cells based on Majority Function and the similarity between the minterms of the (Cout) over bar and Sum functions, are proposed. The cells offer higher speed and less Power-Delay Product (PDP) than the conventional and current implementations of the 1-bit Full Adder cells especially in low voltages. All the input patterns are used for simulation to obtain the delay and the power consumption parameters. Simulations demonstrate improvement in terms of PDP and significant improvement in terms of speed.
引用
收藏
页码：744 / 749
页数：6
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