Design and Implementation of an Ultra Low Power RSA Coprocessor

This paper describes the design and implementation of an ultra low power RSA coprocessor. By improving the Montgomery's algorithm, and using several low power techniques on the design of the RSA coprocessor, this paper has designed a RSA coprocessor with ultra low power consumption and high performance. The RSA coprocessor is implemented using TSMC 0.18um CMOS technology in one of the ZTEIC Corporation's intellectual cards. It can execute 512bit/ 1024bit/ 2048bit RSA modular exponentiations. When executing 1024bit RSA operations, the throughput is about 107.5kbps at 200MHz clock. When executing 2048bit RSA operations, the throughput is about 57kbps at 200Mhz. It's maximum power consumption is 32.5mW when executing 2048bit RSA modular exponentiation.