FPGA implementation of RSA public-key cryptographic coprocessor

被引：0
|
作者：
Hani, MK [1 ]
Lin, TS [1 ]
Shaikh-Husin, N [1 ]
机构：
[1] Univ Teknol Malaysia, Fac Elect Engn, MiCE Dept, Skudai, Johor, Malaysia
来源：
IEEE 2000 TENCON PROCEEDINGS, VOLS I-III: INTELLIGENT SYSTEMS AND TECHNOLOGIES FOR THE NEW MILLENNIUM | 2000年
关键词：
RSA algorithm; Montgomery algorithm; systolic array architecture; FPGA;
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
The hardware implementation of the RSA algorithm for public-key cryptography is presented. The algorithm is dependent on the computation of modular exponentials. Critical to this computation is a fast implementation of modular multiplications. A highperformance systolic array architecture for modular multiplication based on the algorithm of P.L. Montgomery is proposed, The design is targeted for implementation in reconfigurable logic, which can yield custom-hardware performance yet maintains all the flexibility of software-based systems. Reconfigurable computing allows the designer to respond, in the prototyping stage, to flaws discovered in implementation or to changes in standards or data formats. We report the issues involved in the preliminary design of the prototype to be fabricated in Altera FLEX10KE series FPGA mounted on a PCI card.
引用
收藏
页码：B6 / B11
页数：6
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