Design and implementation of an RSA public-key cryptosystem

This paper presents a new bit-serial systolic array for realizing a modified Montgomery algorithm for modular multiplication. The proposed array is highly regular, modular, and thus well suited to be implemented using VLSI techniques. It does not involve any broadcasting signals and thus can be operated at a higher clock rate than existing designs. A VLSI architecture for modular exponentiation, which can be used to implement the encryption, decryption, and digital signature of an RSA public-key cryptosystem, is also constructed based on the proposed modular multiplier. For the purpose of verification, a prototype chip of a 512-bit RSA public-key cryptosystem is designed based on the high-performance COMPASS 0.6 mu m standard cell library. The gate count of the chip is about 132k and the die size is about 8280 mu m x 8224.8<(mu)over bar>m. With an estimated clock rate of 133 MHz a baud rate of 278k bits/sec can be achieved.