Architectures, stability and optimization for clock distribution networks

被引:2
|
作者
Carareto, Rodrigo [1 ]
Orsatti, Fernando M. [1 ]
Piqueira, Jose Roberto C. [1 ]
机构
[1] Univ Sao Paulo, Escola Politecn, BR-05508900 Sao Paulo, Brazil
关键词
Phase-locked loops; Synchronism quality; Tracking time; Voltage-control oscillator; DOUBLE-FREQUENCY JITTER; SYNCHRONIZATION; RECOGNITION;
D O I
10.1016/j.cnsns.2011.08.018
中图分类号
O29 [应用数学];
学科分类号
070104 ;
摘要
Synchronous telecommunication networks, distributed control systems and integrated circuits have its accuracy of operation dependent on the existence of a reliable time basis signal extracted from the line data stream and acquirable to each node. In this sense, the existence of a sub-network (inside the main network) dedicated to the distribution of the clock signals is crucially important. There are different solutions for the architecture of the time distribution sub-network and choosing one of them depends on cost, precision, reliability and operational security. In this work we expose: (i) the possible time distribution networks and their usual topologies and arrangements. (ii) How parameters of the network nodes can affect the reachability and stability of the synchronous state of a network. (iii) Optimizations methods for synchronous networks which can provide low cost architectures with operational precision, reliability and security. (C) 2011 Elsevier B. V. All rights reserved.
引用
收藏
页码:4672 / 4682
页数:11
相关论文
共 50 条
  • [21] Optimization of regulatory architectures in metabolic reaction networks
    Hatzimanikatis, V
    Floudas, CA
    Bailey, JE
    BIOTECHNOLOGY AND BIOENGINEERING, 1996, 52 (04) : 485 - 500
  • [22] Inductance enhancement in global clock distribution networks
    Luman, H
    Davis, J
    PROCEEDINGS OF THE IEEE 2004 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2004, : 119 - 121
  • [23] A Study of Reliability Issues in Clock Distribution Networks
    Todri, Aida
    Marek-Sadowska, Malgorzata
    2008 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 2008, : 101 - 106
  • [24] EMI Reduction by Resonant Clock Distribution Networks
    Mesgarzadeh, Behzad
    Alvandpour, Atila
    2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 977 - 980
  • [25] Reduced Voltage Scaling in Clock Distribution Networks
    Mohammad, Khader
    Dodin, Ayman
    Liu, Bao
    Agaian, Sos
    VLSI DESIGN, 2009, 2009
  • [26] PARTITIONING AND OPTIMIZATION OF HIGH LEVEL STREAM APPLICATIONS FOR MULTI CLOCK DOMAIN ARCHITECTURES
    Brunet, S. Casale
    Bezati, E.
    Alberti, C.
    Mattavelli, M.
    Amaldi, E.
    Janneck, J. W.
    2013 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 2013, : 177 - 182
  • [27] An Evolutionary Optimization Framework for Neural Networks and Neuromorphic Architectures
    Schuman, Catherine D.
    Plank, James S.
    Disney, Adam
    Reynolds, John
    2016 INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS (IJCNN), 2016, : 145 - 154
  • [28] Novel SET Mitigation Technique for Clock Distribution Networks
    Hao, Peipei
    Chen, Shuming
    Huang, Pengcheng
    Chen, Jianjun
    Liang, Bin
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2018, 18 (01) : 105 - 113
  • [29] Power dissipation in basic global clock distribution networks
    Sobczyk, Artur L.
    Luczyk, Arkadiusz W.
    Pleskacz, Witold A.
    PROCEEDINGS OF THE 2007 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2007, : 231 - +
  • [30] HCDN: Hybrid-Mode Clock Distribution Networks
    Islam, Riadul
    Guthaus, Matthew R.
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019, 66 (01) : 251 - 262