Environment for fault simulation acceleration on FPGA

被引：0

作者：

Ellervee, P ^{[1
]}

Raik, J ^{[1
]}

Tihhomirov, V ^{[1
]}

机构：

[1] Tallim Univ Technol, Dept Comp Engn, Tallinn, Estonia

来源：

BEC 2004: PROCEEDING OF THE 9TH BIENNIAL BALTIC ELECTRONICS CONFERENCE | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present an environment to accelerate fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. We studied the feasibility of using reconfigurable hardware emulator instead of software simulation. Experiments showed that it is beneficial to use emulation for circuits/methods that require large numbers of test vectors, e.g., sequential circuits and/or genetic algorithms.

引用

页码：217 / 220

页数：4

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