Design of High performance and Low Power 16T Full Adder Cell for Sub-threshold Technology

被引：0

作者：

Pakniyat, Ebrahim ^{[1
]}

Talebiyan, Seyyed Reza ^{[1
]}

Morad, Milad Jalalian Abbasi ^{[1
]}

机构：

[1] Imam Reza Int Univ, Dept Elect Engn, Mashhad, Iran

来源：

SECOND INTERNATIONAL CONGRESS ON TECHNOLOGY, COMMUNICATION AND KNOWLEDGE (ICTCK 2015) | 2015年

关键词：

1-bit full adder; sub-threshold voltage technology; propagation delay; power consumption;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper presents a new structure of 1-bit full adder for sub-threshold technology. It compares full adder sub-circuits and also compares the proposed full adder with common full adders in terms of propagation delay, power consumption, power delay product and square power delay product in subthreshold technology. HSPICE simulations show that the power dissipation, power delay product and square power delay product of the proposed 16T full adder is 7%, 19% and 25% better than the best common full adder TG, respectively. The full adder circuits are compared in 260 (mV) supply voltage.

引用

页码：79 / 85

页数：7

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