Design of high-performance low-power full adder

被引：4

作者：

Nehru, K. ^{[1
]}

Shanmugam, A. ^{[1
]}

机构：

[1] RMD Engn Coll, Dept Elect & Commun Engn, Chennai 601206, Tamil Nadu, India

来源：

INTERNATIONAL JOURNAL OF COMPUTER APPLICATIONS IN TECHNOLOGY | 2014年 / 49卷 / 02期

关键词：

low power; full adders; VLSI; very large scale integration; XOR gate;

D O I：

10.1504/IJCAT.2014.060524

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

Full adder is an essential component for the design and development of all types of processor. This project introduces the design of high-performance low-power full adder which acquires least area with the lowest transistor count. The high-performance low-power full adder is designed and the implementation of a 32-bit ripple carry adder based on high-performance low-power full adder circuit is described, and comparison is made with other previously designed full adders. The high-performance low-power full adder circuit is designed and the simulation has been carried out on Tanner EDA tool. The result shows that the proposed high-performance low-power full adder is an efficient full adder cell with least MOS transistor count that reduces the high power consumption and considerably increases the speed.

引用

页码：134 / 140

页数：7

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