Formal Analysis of the ACE Specification for Cache Coherent Systems-on-Chip

被引：0

作者：

Kriouile, Abderahman ^{[1
,2
]}

Serwe, Wendelin ^{[2
]}

机构：

[1] STMicroelectronics, 12 Rue Jules Horowitz,BP 217, F-38019 Grenoble, France

[2] INRIA, LIG, F-38334 Saint Ismier, France

来源：

FORMAL METHODS FOR INDUSTRIAL CRITICAL SYSTEMS | 2013年 / 8187卷

关键词：

VERIFICATION;

D O I：

暂无

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

System-on-Chip (SoC) architectures integrate now many different components, such as processors, accelerators, memory, and I/O blocks, some but not all of which may have caches. Because the validation effort with simulation-based validation techniques, as currently used in industry, grows exponentially with the complexity of the SoC, we investigate in this paper the use of formal verification techniques. More precisely, we use the CADP toolbox to develop and validate a generic formal model of an SoC compliant with the recent ACE specification proposed by ARM to implement system-level coherency.

引用

页码：108 / 122

页数：15

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