Memory Architectures for embedded systems-on-chip

被引：0
|
作者：
Panda, PR
Dutt, ND
机构：
[1] Indian Inst Technol, Dept Comp Sci & Engn, New Delhi 110016, India
[2] Univ Calif Irvine, Ctr Embedded Comp Syst, Irvine, CA 92697 USA
来源：
HIGH PERFORMANCE COMPUTING - HIPC 2002, PROCEEDINGS | 2002年 / 2552卷
关键词：
D O I：
暂无
中图分类号：
TP31 [计算机软件];
学科分类号：
081202 ; 0835 ;
摘要：
Embedded systems are typically designed for one or a few target applications, allowing for customization of the system architecture for the desired system goals such as performance, power and cost. The memory subsystem will continue to present significant bottlenecks in the design of future embedded systems-on-chip. Using advance knowledge of the application's instruction and data behavior, it is possible to customize the memory architecture to meet varying system goals. On one hand, different applications exhibit varying memory behavior. On the other hand, a large variety of memory modules allow design implementations with a wide range of cost, performance and power profiles. The embedded system architect can thus explore and select custom memory architectures to fit the constraints of target applications and design goals. In this paper we present an overview of recent research in the area of memory architecture customization for embedded systems.
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收藏
页码：647 / 662
页数：16
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