Non-enumerative Generation of Path Delay Distributions and Its Application to Critical Path Selection

被引：2

作者：

Somashekar, Ahish Mysore ^{[1
]}

Tragoudas, Spyros ^{[1
]}

Jayabharathi, Rathish ^{[2
]}

Gangadhar, Sreenivas ^{[3
]}

机构：

[1] Southern Illinios Univ, Elect & Comp Engn Dept, 1230 Lincoln Dr, Carbondale, IL 62901 USA

[2] Intel Corp, 1900 Prarie City Rd, Folsom, CA 95630 USA

[3] Intel Corp, 1300 S MoPac Expy, Austin, TX 78746 USA

来源：

ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS | 2016年 / 22卷 / 01期

基金：

美国国家科学基金会;

关键词：

Delay estimation; timing analysis; silicon debug; critical paths; Monte Carlo; zero-suppressed binary decision diagrams (ZBDDs); LONGEST TESTABLE PATHS; TIMING ANALYSIS; FAULTS; IDENTIFICATION;

D O I：

10.1145/2940327

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A Monte Carlo-based approach is proposed capable of identifying in a non-enumerative and scalable manner the distributions that describe the delay of every path in a combinational circuit. Furthermore, a scalable approach to select critical paths from a potentially exponential number of path candidates is presented. Paths and their delay distributions are stored in Zero Suppressed Binary Decision Diagrams. Experimental results on some of the largest ISCAS-89 and ITC-99 benchmarks shows that the proposed method is highly scalable and effective.

引用

页数：21

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