Through-Silicon Via Technology for Three-Dimensional Integrated Circuit Manufacturing

被引：0

作者：

Civale, Yann ^{[1
]}

Redolfi, Augusto ^{[1
]}

Jaenen, Patrick ^{[1
]}

Kostermans, Maarten ^{[1
]}

Van Besien, Els ^{[1
]}

Mertens, Sofie ^{[1
]}

Witters, Thomas ^{[1
]}

Jourdan, Nicolas ^{[1
]}

Armini, Silvia ^{[1
]}

El-Mekki, Zaid ^{[1
]}

Vandersmissen, Kevin ^{[1
]}

Philipsen, Harold ^{[1
]}

Verdonck, Patrick ^{[1
]}

Heylen, Nancy ^{[1
]}

Nolmans, Philip ^{[1
]}

Li, Yunlong ^{[1
]}

Croes, Kristof ^{[1
]}

Beyer, Gerald ^{[1
]}

Swinnen, Bart ^{[1
]}

Beyne, Eric ^{[1
]}

机构：

[1] IMEC, B-3001 Louvain, Belgium

来源：

2012 35TH IEEE/CPMT INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM (IEMT) | 2012年

关键词：

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Higher performance, higher operation speed and volume shrinkage require high 3D TSV interconnect densities. This work focuses on a via-middle 3D process flow, which implies processing of the 3D-TSV after the front-end-of-line (FEOL) and before the back-end-of-line (BEOL) interconnect process. A description of the imec 300 mm TSV platform is given, and challenges towards a reliable process integration of high density high aspect-ratio 3D interconnections are also discussed in details.

引用

页数：5

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