A New Asymmetric Multilevel Inverter with Reduced Number of Switches and Reduction of Harmonics using Sine Property

被引：0
|
作者：
Kumar, A. Rakesh [1 ]
Deepa, T. [1 ]
机构：
[1] VIT Univ, SELECT, Chennai, Tamil Nadu, India
来源：
PROCEEDINGS OF IEEE INTERNATIONAL CONFERENCE ON CIRCUIT, POWER AND COMPUTING TECHNOLOGIES (ICCPCT 2016) | 2016年
关键词：
H Bridge; Harmonics; Inverter; Sine Property; Topology; PERFORMANCE;
D O I：
暂无
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
In this paper, a new topology named OTF (One-Two-Five) topology is proposed for an asymmetrical multilevel inverter. The OTF topology is implemented with less number of switches compared with other conventional and recently invented topologies. The reduction of switches leads to low cost of the inverter. The reduction of the switches is usually associated with more number of levels achieved and reduced harmonic content. Sine Property is reviewed with the proposed topology to reduce the harmonics content. Simulation is performed for a 17 level inverter of the proposed topology using MATLAB/SIMULINK. Fast Fourier Transformation (FFT) analysis is performed and the results are verified.
引用
收藏
页数：8
相关论文
共 50 条
  • [1] A New Hybrid Asymmetric Multilevel Inverter with Reduced Number Of Switches
    Prabaharan, N.
    Palanisamy, K.
    2016 IEEE INTERNATIONAL CONFERENCE ON POWER ELECTRONICS, DRIVES AND ENERGY SYSTEMS (PEDES), 2016,
  • [2] Asymmetric Multilevel Hybrid Inverter with Reduced Number of Switches
    Abraham, Babitha T.
    Benny, Anish
    2014 ANNUAL INTERNATIONAL CONFERENCE ON EMERGING RESEARCH AREAS: MAGNETICS, MACHINES AND DRIVES (AICERA/ICMMD), 2014,
  • [3] New Single Phase Asymmetric Multilevel Inverter with Reduced Number of Power Switches
    Thiyagarajan, V
    Somasundaram, P.
    2017 INTERNATIONAL CONFERENCE ON POWER AND EMBEDDED DRIVE CONTROL (ICPEDC), 2017, : 219 - 222
  • [4] The New Topology of Multilevel Inverter with Reduced Number of Switches
    Jefry, Nur Atiqah
    Haw, Law Kah
    Ing, Wong Kiing
    2020 11TH IEEE CONTROL AND SYSTEM GRADUATE RESEARCH COLLOQUIUM (ICSGRC), 2020, : 94 - 99
  • [5] Simulation of New Symmetric and. Asymmetric Multilevel Inverter Topology with Reduced Number of Switches
    Thiyagarajan, V.
    Somasundaram, P.
    2018 4TH INTERNATIONAL CONFERENCE ON ELECTRICAL ENERGY SYSTEMS (ICEES), 2018, : 315 - 319
  • [6] Multilevel inverter with reduced number of switches
    Koshti, Amol K.
    Thorat, A. R.
    Bhattar, P. C. Tejasvi. L.
    PROCEEDINGS OF 2017 IEEE INTERNATIONAL CONFERENCE ON CIRCUIT ,POWER AND COMPUTING TECHNOLOGIES (ICCPCT), 2017,
  • [7] Novel symmetric and asymmetric topology of multilevel inverter with reduced number of switches
    Reddy, Kelam Bala Muralidhar
    Pattnaik, Swapnajit
    2017 IEEE INTERNATIONAL CONFERENCE ON INDUSTRIAL TECHNOLOGY (ICIT), 2017, : 165 - 170
  • [8] Simulation Analysis of New Multilevel Inverter with Reduced Number of Switches
    Dhivakar, K.
    Thiyagarajan, V
    2018 4TH INTERNATIONAL CONFERENCE ON ELECTRICAL ENERGY SYSTEMS (ICEES), 2018, : 443 - 448
  • [9] A New Multilevel Inverter Topology with Reduced Number of Power Switches
    Beigi, L. M. A.
    Azli, N. A.
    Khosravi, F.
    Najafi, E.
    Kaykhosravi, A.
    2012 IEEE INTERNATIONAL CONFERENCE ON POWER AND ENERGY (PECON), 2012, : 55 - 59
  • [10] A New Asymmetric Multilevel Inverter With Reduced Number of Components
    Yousofi-Darmian, Saeed
    Masoud Barakati, S.
    IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, 2020, 8 (04) : 4333 - 4342
12345