共 50 条
- [42] The Design Method of Logic Circuits based on the Voltage-Input Enhanced Scouting Logic Gates 2022 32ND INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, FPL, 2022, : 136 - 142
- [43] Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates IEEE ACCESS, 2019, 7 : 163939 - 163947
- [47] Design of Computing Circuits using Spatially Localized DNA Majority Logic Gates 2017 IEEE INTERNATIONAL CONFERENCE ON REBOOTING COMPUTING (ICRC), 2017, : 314 - 320
- [48] Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits MICROELECTRONICS JOURNAL, 2016, 53 : 156 - 166