Design of reversible logic circuits by means of control gates

被引:0
|
作者
De Vos, A [1 ]
Desoete, B
Adamski, A
Pietrzak, P
Sibinski, M
Widerski, T
机构
[1] Univ Gent & Imec VZW, B-9000 Ghent, Belgium
[2] Univ Ghent, B-9000 Ghent, Belgium
[3] Tech Univ Lodz, PL-90924 Lodz, Poland
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A design methodology for reversible logic circuits is presented. Any boolean function can be built using the three fundamental building blocks of Feynman. The implementation of these logic gates into electronic circuitry is based on c-MOS technology and pass-transistor design. We present a chip containing single Feynman gates, as well as an application: a chip containing a fully reversible four-bit adder. We propose a generalization of the Feynman gates: the reversible control gates.
引用
收藏
页码:255 / 264
页数:10
相关论文
共 50 条
  • [41] Design of all-optical reversible logic gates using photonic crystal waveguides for optical computing and photonic integrated circuits
    Rao, Dalai Gowri Sankar
    Swarnakar, Sandip
    Kumar, Santosh
    APPLIED OPTICS, 2020, 59 (35) : 11003 - 11012
  • [42] The Design Method of Logic Circuits based on the Voltage-Input Enhanced Scouting Logic Gates
    Liu, Fan
    Zhang, Sunrui
    Cui, Xiaole
    2022 32ND INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, FPL, 2022, : 136 - 142
  • [43] Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates
    Parvin, Sajjad
    Altun, Mustafa
    IEEE ACCESS, 2019, 7 : 163939 - 163947
  • [44] Synthesis of reversible logic circuits
    Shende, VV
    Prasad, AK
    Markov, IL
    Hayes, JP
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2003, 22 (06) : 710 - 722
  • [45] One-Pass Design of Reversible Circuits: Combining Embedding and Synthesis for Reversible Logic
    Zulehner, Alwin
    Wille, Robert
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 37 (05) : 996 - 1008
  • [46] A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits
    Tena-Sanchez, Erica
    Castro, Javier
    Acosta, Antonio J.
    IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, 2014, 4 (02) : 203 - 215
  • [47] Design of Computing Circuits using Spatially Localized DNA Majority Logic Gates
    George, Aby K.
    Singh, Harpreet
    2017 IEEE INTERNATIONAL CONFERENCE ON REBOOTING COMPUTING (ICRC), 2017, : 314 - 320
  • [48] Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits
    Ebrahimi, Seyyed Ashkan
    Reshadinezhad, Mohammad Reza
    Bohlooli, Ali
    Shahsavari, Mahyar
    MICROELECTRONICS JOURNAL, 2016, 53 : 156 - 166
  • [49] ON THE DESIGN OF CMOS TERNARY LOGIC-CIRCUITS USING T-GATES
    CHEW, BP
    MOUFTAH, HT
    INTERNATIONAL JOURNAL OF ELECTRONICS, 1987, 63 (02) : 229 - 239
  • [50] DESIGN OF TERNARY LOGIC CIRCUITS USING M-NAND AND NOT GATES.
    Odaka, Akio
    Satoh, Kunio
    1600, (16):