Fast C-testable array multipliers

被引:4
|
作者
Gizopoulos, D [1 ]
Nikolos, D [1 ]
Paschalis, A [1 ]
机构
[1] UNIV PATRAS,DEPT COMP ENGN & INFORMAT,GR-26500 PATRAI,GREECE
关键词
D O I
10.1080/002072196137192
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Many C-testable designs of parallel array multipliers have been presented in the open literature in the last few years. All these designs use slow ripple-carry addition at the last stage of the multiplier to form the final product. However, practical multiplier implementations use fast adders (like carry lookahead adders) at the last stage to speed up the multiplication process. In this paper, C-testable M x N carry-save array multipliers with carry lookahead adders in the last stage are presented. Depending on the use of the standard CLA adder block or a new modified CLA adder block, the test sets for the proposed C-testable multipliers consist of 34 and 30 vectors, respectively, while the number of required extra primary inputs is only one in both cases. A graph-based method is introduced to apply the required test vectors to the final CLA adder. Both the hardware and delay overhead of our C-testable designs are very small and decrease with increasing operand lengths.
引用
收藏
页码:561 / 582
页数:22
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