Influence of body contact on the ESD protection performance in 0.35μm Partially-Depleted SOI Salicided CMOS Technology

被引：0

作者：

Wang, Zhongfang ^{[1
]}

Xie, Chengmin ^{[1
]}

Yue, Hongju ^{[1
]}

Wu, Longsheng ^{[1
]}

Liu, Youbao ^{[1
]}

机构：

[1] Xian Microelect Tech Inst, Comp Res & Design Dept, Xian, Peoples R China

来源：

MANUFACTURING SCIENCE AND TECHNOLOGY, PTS 1-8 | 2012年 / 383-390卷

关键词：

body contact; ESD protection; floating body effect; H gate structure; BTS structure; SUPPRESSION; MOSFETS;

D O I：

10.4028/www.scientific.net/AMR.383-390.7025

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

Although body contact can solve the problem of floating body effect in the partially-depleted (PD) SOI technology, it still has important influence on the ESD protection performance. In order to investigate the influence of body contact on the ESD protection performance, three different structures are fabricated in 0.35 mu m PD SOI salicided CMOS technology, they are stick gate structure with body floating, H gate structure with body contact located outside the edge gate, and body tied source (BTS)structure with body contact placed intermittently along the source diffusion. The transmission line pulse generator(TLPG) measured results of these three different structures are compared and analyzed, both the stick gate structure with body floating and BTS structure have a better robustness level than H gate structure with body contact.

引用

页码：7025 / 7031

页数：7

共 33 条

[11] Effects of SOI film thickness on high-performance microprocessor by 0.13μm partially-depleted SOICMOS technology
Yang, J
Min, B
Yasuhito, S
Kang, L
Walker, P
Mendicino, M
Yeap, G
Foisy, M
Cox, K
Cartwright, J
Venkatesan, S
2003 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2003, : 41 - 42
[12] ESD implantations in 0.18-μm salicided CMOS technology for on-chip ESD protection with layout consideration
Ker, MD
Chuang, CH
PROCEEDINGS OF THE 2001 8TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS, 2001, : 85 - 90
[13] ESD implantations for on-chip ESD protection with layout consideration in 0.18-μm salicided CMOS technology
Ker, MD
Chuang, CH
Lo, WY
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2005, 18 (02) : 328 - 337
[14] A CAD-compatible SOI/CMOS gate array having body-fixed partially-depleted transistors
Ueda, K
Nii, K
Wada, Y
Takimoto, I
Maeda, S
Iwamatsu, T
Yamaguchi, Y
Maegawa, S
Mashiko, K
Hamano, H
1997 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - DIGEST OF TECHNICAL PAPERS, 1997, 40 : 288 - 289
[15] Comparison of different on-chip ESD protection structures in a 0.35 μm CMOS technology
Richier, C.
Maene, N.
Mabboux, G.
Bellens, R.
Microelectronics Reliability, 1997, 37 (10-11): : 1537 - 1540
[16] Comparison of different on-chip ESD protection structures in a 0.35 mu m CMOS technology
Richier, C
Maene, N
Mabboux, G
Bellens, R
MICROELECTRONICS AND RELIABILITY, 1997, 37 (10-11): : 1537 - 1540
[17] Efficacy of body ties under dynamic switching conditions in partially depleted SOI CMOS technology
Krishnan, S
1997 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS, 1996, : 140 - 141
[18] DC and large-signal microwave MOSFET model applicable to partially-depleted, body-contacted SOI technology
Burke, Darren R.
El Kaamouchi, Maiid
Vanhoenacker-Janvier, Danielle
Brazil, Thomas J.
2007 IEEE/MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-6, 2007, : 585 - 588
[19] High performance SRAMs IN 1.5 V, 0.18μm partially depleted SOI technology
Joshi, RV
Pellela, A
Wagner, O
Chan, YH
Dachtera, W
Wilson, S
Kowalczyk, SP
2002 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2002, : 74 - 77
[20] Efficient Characterization Methodology of Gate-Bulk Leakage and Capacitance for Ultra-Thin Oxide Partially-Depleted (PD) SOI Floating Body CMOS
Chen, David
Lee, Ryan
Liu, Y. C.
Lin, Guan Shyan
Tang, Mao Chyuan
Wang, Meng Fan
Yeh, C. S.
Chien, S. C.
ICMTS 2009: 2009 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, 2009, : 133 - 136

← 1 2 3 4 →