A CAD-compatible SOI/CMOS gate array having body-fixed partially-depleted transistors

被引：1
|
作者：
Ueda, K
Nii, K
Wada, Y
Takimoto, I
Maeda, S
Iwamatsu, T
Yamaguchi, Y
Maegawa, S
Mashiko, K
Hamano, H
机构：
来源：
1997 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - DIGEST OF TECHNICAL PAPERS | 1997年 / 40卷
关键词：
D O I：
10.1109/ISSCC.1997.585386
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：288 / 289
页数：2
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