Hardware reduction in digital MASH delta-sigma modulators via error masking

被引：0
|
作者：
Ye, Zhipeng [1 ]
Kennedy, Michael Peter [1 ]
机构：
[1] Natl Univ Ireland Univ Coll Cork, Dept Microelect Engn, Cork, Ireland
来源：
PRIME: 2008 PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS, PROCEEDINGS | 2008年
基金：
爱尔兰科学基金会;
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A reduced complexity (RC) digital Multi-stAge noise SHaping (MASH) delta-sigma modulator (DSM) was proposed in [1]. The sequence length is maximized by setting the LSB of the input to "1"; a long word is used for the first modulator in a MASH structure; shorter words are used in subsequent stages. Rules for selecting the wordlengths of each stage are presented in this paper. We show that an appropriate selection of the wordlength for each stage of the DSM can yield similar performance compared with a conventional MASH DSM, but with less hardware and lower power consumption.
引用
收藏
页码：241 / 244
页数：4
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