Bonding Based Channel Transfer and Low Temperature Process for Monolithic 3D Integration Platform Development

被引：0

作者：

Choi, Rino ^{[1
]}

Yu, Hyun-Yong ^{[2
]}

Kim, Hyungsub ^{[3
]}

Ryu, Han-Youl ^{[4
]}

Bae, Hee-Kyung ^{[5
]}

Choi, Kevin Kinam ^{[6
]}

Cha, Yong-Won ^{[6
]}

Choi, Changhwan ^{[7
]}

机构：

[1] Inha Univ, Dept Mat Sci & Engn, Incheon 402751, South Korea

[2] Korea Univ, Sch Elect Engn, Seoul 136701, South Korea

[3] Sungkyunkwan Univ, Sch Adv Mat Sci & Engn, Suwon 16419, South Korea

[4] Inha Univ, Dept Phys, Incheon 402751, South Korea

[5] Natl NanoFab Ctr NNFC, Daejon 34141, South Korea

[6] The Bondis, Hwaseong 18449, South Korea

[7] Hanyang Univ, Div Mat Sci & Engn, Seoul 04763, South Korea

来源：

2016 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S) | 2016年

基金：

新加坡国家研究基金会;

关键词：

Monolithic; 3D; Low Temperature Bonding; Epitaxial Growth; Gate Stack; Laser Annealing;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have studied low temperature processes for monolithic 3D integration platform development including hydrogen/helium ion implantation-based wafer cleavage & bonding (<450 degrees C), low temperature (<550 degrees C) in-situ doped S/D selective SiGe epi process, low temperature (<200 degrees C) gate stack on the chemical-mechanical polished (CMP) wafer, and green-lased annealing. These unit technologies can be adopted to achieve 3D integration platform technology for the high performance and low power applications.

引用

页数：2

共 50 条

[1] Low Temperature Bonding Technology Development for 3D and Heterogeneous Integration
Chen, Kuan-Neng
2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 79 - 79
[2] Low temperature bonding for 3D integration FOREWORD
Fujino, Masahisa
JAPANESE JOURNAL OF APPLIED PHYSICS, 2022, 61 (SF)
[3] Low temperature bonding technology for 3D integration
Ko, Cheng-Ta
Chen, Kuan-Neng
MICROELECTRONICS RELIABILITY, 2012, 52 (02) : 302 - 311
[4] Low Temperature Bonding for 3D Integration FOREWORD
Shigekawa, Naoteru
Takagi, Hideki
Fujino, Masahisa
Higurashi, Eiji
Nishiyama, Nobuhiko
Shimatsu, Takehito
Toyoda, Noriaki
JAPANESE JOURNAL OF APPLIED PHYSICS, 2020, 59 (SB)
[5] Low Temperature Cu/In Bonding for 3D Integration
Panchenko, Iuliana
Bickel, Steffen
Meyer, Joerg
Mueller, Maik
Wolf, Juergen M.
2017 5TH INTERNATIONAL WORKSHOP ON LOW TEMPERATURE BONDING FOR 3D INTEGRATION (LTB-3D), 2017, : 17 - 17
[6] Low Temperature Bonding for 3D Integration FOREWORD
Suga, Tadatomo
Shigekawa, Naoteru
Higurashi, Eiji
Shimatsu, Takehito
Sugiyama, Masakazu
Takagi, Hideki
Toyoda, Noriaki
JAPANESE JOURNAL OF APPLIED PHYSICS, 2018, 57 (02)
[7] Germanium Layer Transfer with Low Temperature Direct Bonding and Epitaxial Lift-off Technique for Ge-based monolithic 3D integration
Maeda, Tatsuro
Ishii, Hiroyuki
Chang, Wen Hsin
Irisawa, Toshifumi
Kurashima, Yuichi
Takagi, Hideki
Uchida, Noriyuki
2019 SILICON NANOELECTRONICS WORKSHOP (SNW), 2019, : 9 - 10
[8] Low Temperature Hybrid Wafer Bonding for 3D Integration
Damian, A. A.
Poelma, R. H.
van Zeijl, H. W.
Zhang, G. Q.
2013 14TH INTERNATIONAL CONFERENCE ON THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICROELECTRONICS AND MICROSYSTEMS (EUROSIME), 2013,
[9] Low Temperature Bonding with Thin Wafers for 3D Integration
Matthias, T.
Kim, B.
Kettner, P.
Wimplinger, M.
Lindner, P.
CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2011 (CSTIC 2011), 2011, 34 (01): : 1023 - 1028
[10] Investigation of Low Temperature Cu/In Bonding in 3D Integration
Hsieh, Yu-Sheng
Shen, Ting-Ting
Chien, Yu-San
Chen, Kuan-Neng
Shinozaki, Yuko
Kawasaki, Naohiko
PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2015, : 383 - 386

← 1 2 3 4 5 →