BANG-BANG CDR'S ACQUISITION, LOCKING, AND JITTER TOLERANCE

被引：0
|
作者：
He, Chao [1 ]
Kwasniewski, Tadeusz [1 ]
机构：
[1] Carleton Univ, DOE, Ottawa, ON K1S 5B6, Canada
来源：
2012 25TH IEEE CANADIAN CONFERENCE ON ELECTRICAL & COMPUTER ENGINEERING (CCECE) | 2012年
关键词：
CDR; integral path; jitter tolerance; proportional path; slewing;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
The CDR (Clock and Data Recovery) using PLL with Bang-Bang PD (Phase Detector), CP (Charge Pump), and RC (Resistor and Capacitor) filter is widely used in Serdes circuits. This paper provides a detailed analysis to Bang-Bang CDR's dynamic behaviors and jitter tolerance. Then the slewing conditions, locking condition, and jitter tolerance curve, which are verified by a model implemented in Simulink, are proposed for choosing the filter parameters when designing the circuits.
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页数：4
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