Convolutional Encoder and Viterbi Decoder Using SOPC For Variable Constraint Length

被引：0

作者：

Kulkarni, Anuradha ^{[1
]}

Mantri, Dnyaneshwar ^{[2
]}

Prasad, Neeli R. ^{[2
]}

Prasad, Ramjee ^{[2
]}

机构：

[1] Sinhgad Inst Technol, Lonavala, India

[2] Aalborg Univ, Ctr TeleInFrastrukt, Aalborg, Denmark

来源：

PROCEEDINGS OF THE 2013 3RD IEEE INTERNATIONAL ADVANCE COMPUTING CONFERENCE (IACC) | 2013年

关键词：

convolution encoder; Viterbi decoder; SOPC; constraint length;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Convolution encoder and Viterbi decoder are the basic and important blocks in any Code Division Multiple Accesses (CDMA). They are widely used in communication system due to their error correcting capability But the performance degrades with variable constraint length. In this context to have detailed analysis, this paper deals with the implementation of convolution encoder and Viterbi decoder using system on programming chip (SOPC). It uses variable constraint length of 7, 8 and 9 bits for 1/2 and 1/3 code rates. By analyzing the Viterbi algorithm it is seen that our algorithm has a better error rate for 1/2 code rates than 1/3. The reduced bit error rate with increasing constraint length shows an increase in efficiency and better utilization of resources as bandwidth and power.

引用

页码：1651 / 1655

页数：5

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