A novel functional testing and verification technique for logic circuits

被引:0
|
作者
Al-Asaad, H [1 ]
Valliappan, G [1 ]
Ramirez, L [1 ]
机构
[1] Univ Calif Davis, Dept Elect & Comp Engn, Davis, CA 95616 USA
关键词
simulation; functional testing/verification; logic circuits; implementation-independent testing;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Functional verification plays a key role in the design verification cycle and the physical fault testing process. There are several functional verification methods that generate tests for modules independent of their implementation; however these methods do not scale well for medium to large circuits. In this paper we introduce a new implementation-independent functional test generation technique that extracts a good set of functional vectors that are characterized by a small number of neighbors. Two input vectors of a function are considered neighbors if they produce the same output value of the function and the Hamming distance between them is one. Our method can be easily implemented and it generates tests by selecting input vectors that have fewer neighbors among all input vectors. Our experimental results demonstrate that our generated tests are significantly better than random tests. Moreover our method can handle multiple-output circuits, and can be easily scaled to target large designs.
引用
收藏
页码:129 / 135
页数:7
相关论文
共 50 条
  • [41] Deriving Approximate Logic Circuits for TMR Technique
    A. Yu. Matrosova
    S. A. Ostanin
    G. G. Goshin
    Russian Physics Journal, 2022, 65 : 751 - 760
  • [42] Novel logic circuits controlled by Vdd
    Sekanina, Lukas
    Starecek, Lukas
    Kotasek, Zdenek
    PROCEEDINGS OF THE 2006 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2006, : 85 - +
  • [43] AN ALGORITHM FOR FUNCTIONAL VERIFICATION OF DIGITAL ECL CIRCUITS
    BRAUER, EJ
    KANG, SM
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1995, 14 (12) : 1546 - 1556
  • [44] How to Use Temporal Logic in Combinational Circuits Verification with SMV
    Kotmanova, Daniela
    INFORMATICS 2013: PROCEEDINGS OF THE TWELFTH INTERNATIONAL CONFERENCE ON INFORMATICS, 2013, : 83 - 87
  • [45] Identify equivalent signal lines for logic verification of combinational circuits
    Pan, Zhongliang
    Chen, Ling
    INFORMATION TECHNOLOGY AND INDUSTRIAL ENGINEERING, VOLS 1 & 2, 2014, : 313 - 320
  • [46] AUTOMATIC VERIFICATION OF SEQUENTIAL-CIRCUITS USING TEMPORAL LOGIC
    BROWNE, MC
    CLARKE, EM
    DILL, DL
    MISHRA, B
    IEEE TRANSACTIONS ON COMPUTERS, 1986, 35 (12) : 1035 - 1044
  • [47] TIMING VERIFICATION OF LOGIC-CIRCUITS WITH COMBINED DELAY MODEL
    KIMURA, S
    KASHIMA, S
    HANEDA, H
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1992, E75A (10) : 1230 - 1238
  • [48] An Equivalence Verification Methodology for Asynchronous Sleep Convention Logic Circuits
    Hossain, Mousam
    Sakib, Ashiq A.
    Srinivasan, Sudarshan K.
    Smith, Scott C.
    2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2019,
  • [49] AUTOMATIC VERIFICATION OF SEQUENTIAL CIRCUITS USING TEMPORAL LOGIC.
    Browne, Michael C.
    Clarke, Edmund M.
    Dill, David L.
    Mishra, Bud
    1600, (C-35):
  • [50] LEVER. A logic extraction and verification program for MOS circuits
    Wang, P.-H.P.
    McNamee, L.
    Proceedings of the ISMM International Symposium Computer Applications in Design, Simulation and Analysis, 1991,