RISC/DSP dual core wireless SoC processor focused on multimedia applications

被引:0
|
作者
Suh, HJ
Kim, J
机构
[1] Catholic Univ Korea, Sch Comp Sci & Informat Engn, Puchon 420743, Gyeonggido, South Korea
[2] GCT Semicond Inc, San Jose, CA 95131 USA
来源
EMBEDDED AND UBIQUITOUS COMPUTING - EUC 2005 | 2005年 / 3824卷
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The key technology of the mobile multimedia application is System-On-Chip processor that integrates the major function unit with low power consumption using a small battery. The wireless communication is practical technology, which makes comfortable communications between devices, such as IEEE 802.11a/b/g and Bluetooth. By the modern streaming technology with compression, like mpeg, the wireless communication triggers high quality media service without wires. The wireless communication spend a quite large portion of energy of mobile device if data flows continuously, hence a delicate energy control may needed to fulfill a saving of the limited energy. Due to these issues, integrating the wireless function units into the high performance embedded processor supports a seamless control of power consumption of wireless part, and the communication data flows are sealed in the SoC chip, which reduces inter-chip communiaction energy between a main processor and a wireless media access controller. We focused the high performance wireless multimedia applications are suffered by the energy consumption, so we alleviated the power issue by integrating of IEEE 802.11a/b/g media access controller, modem, ADC/DAC, high performance DSP, and RISC core in a silicon. We present a wireless capable SoC processor, GDM5104, that integrated the multiple wireless media access controller as well as CCK/OFDM/GFSK modem and ADC/DAC also. Furthermore, the processor integrates RISC and DSP independent cores with appropriate caches, and rich peripherals that sufficient to implement mobile multimedia applications, hence the processor exhibits wireless connectivity with low power consumption. The processor is fabricated in a 0.18um standard CMOS technology, and operates at 133MHz RISC, and 100MHz DSP, which provides full capability of wireless multimedia processing.
引用
收藏
页码:321 / 330
页数:10
相关论文
共 50 条
  • [31] Scalable motion estimation processor core for multimedia system-on-chip applications
    Lai, Yeong-Kang
    Hsieh, Tian-En
    Chen, Lien-Fei
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2007, 46 (4B): : 2238 - 2243
  • [32] Scalable motion estimation processor core for multimedia system-on-chip applications
    Lai, Yeong-Kang
    Hsieh, Tian-En
    Chen, Lien-Fei
    Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 2007, 46 (4 B): : 2238 - 2243
  • [33] DITES: A Lightweight and Flexible Dual-Core Isolated Trusted Execution SoC Based on RISC-V
    Chen, Yuehai
    Chen, Huarun
    Chen, Shaozhen
    Han, Chao
    Ye, Wujian
    Liu, Yijun
    Zhou, Huihui
    SENSORS, 2022, 22 (16)
  • [34] Tera-scale Performance Machine Learning SoC with Dual Stream Processor Architecture for Multimedia Content Analysis
    Chen, Tse-Wei
    Tang, Chi-Sun
    Tsai, Sung-Fang
    Tsai, Chen-Han
    Chien, Shao-Yi
    Chen, Liang-Gee
    PROCEEDINGS OF THE IEEE 2009 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2009, : 491 - +
  • [35] Realization of embedded multimedia system based on dual-core processor OMAP5910
    Li, Peng
    Lu, Yu
    Wei, Hongxing
    Li, Shen
    2006 IMACS: MULTICONFERENCE ON COMPUTATIONAL ENGINEERING IN SYSTEMS APPLICATIONS, VOLS 1 AND 2, 2006, : 101 - 105
  • [36] Distributed object models for multi-processor SoC's, with application to low-power multimedia wireless systems
    Paulin, Pierre G.
    Pilkington, Chuck
    Langevin, Michel
    Bensoudane, Essaid
    Benny, Olivier
    Lyonnard, Damien
    Lavigueur, Bruno
    Lo, David
    2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS, 2006, : 480 - +
  • [37] A 65nm Dual-mode Baseband and Multimedia Application Processor SoC with Advanced Power and Memory Management
    Kamei, Tatsuya
    Yamada, Tetsuhiro
    Koike, Takao
    Ito, Masayuki
    Irita, Takahiro
    Nitta, Kenichi
    Hattori, Toshihiro
    Yoshioka, Shinichi
    PROCEEDINGS OF THE ASP-DAC 2009: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2009, 2009, : 535 - 539
  • [38] Enabling multimedia applications in 2.5G and 3G wireless terminals through a combined RISC/DSP architecture: OMAPOMAP: eine neuartige RISC/DSP-Achitektur für künftige Multimedia-Anwendungen in 2.5G- und 3G-Mobiltelefonen
    J. Chaoui
    K. Cyr
    S. De Gregorio
    B. Cornillault
    J. -P. Giacalone
    J. Webb
    Y. Masse
    e & i Elektrotechnik und Informationstechnik, 2003, 120 (2) : 66 - 68
  • [39] Tera-Scale Performance Machine Learning SoC (MLSoC) With Dual Stream Processor Architecture for Multimedia Content Analysis
    Chen, Tse-Wei
    Tang, Chi-Sun
    Tsai, Sung-Fang
    Tsai, Chen-Han
    Chien, Shao-Yi
    Chen, Liang-Gee
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45 (11) : 2321 - 2329
  • [40] Implementation of an Embedded Dual-Core Processor for Portable Medical Electronics Applications
    Chen, Yingrui
    Wang, Teng
    Wang, Xin'an
    Hu, Ziyi
    2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2013,