Viterbi Accelerator for Embedded Processor Datapaths

被引：0

作者：

Azhar, Muhammad Waqar ^{[1
]}

Sjalander, Magnus ^{[1
]}

Ali, Hasan ^{[1
]}

Vijayashekar, Akshay ^{[1
]}

Tung Thanh Hoang ^{[1
]}

Ansari, Kashan Khurshid ^{[1
]}

Larsson-Edefors, Per ^{[1
]}

机构：

[1] Chalmers Univ Technol, VLSI Res Grp, Dept Comp Sci & Engn, S-41296 Gothenburg, Sweden

来源：

2012 IEEE 23RD INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP) | 2012年

关键词：

DECODER; IMPLEMENTATION; FLEXIBILITY; POWER;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present a novel architecture for a lightweight Viterbi accelerator that can be tightly integrated inside an embedded processor datapath. We investigate the accelerator's impact on processor performance by using the EEMBC Viterbi benchmark and the in-house Viterbi Branch Metric kernel. Our evaluation based on the EEMBC benchmark shows that an accelerated 65-nm 2.7-ns processor datapath is 20% larger but 90% more cycle efficient than a datapath lacking the Viterbi accelerator, leading to an 87% overall energy reduction and a data throughput of 3.52 Mbit/s.

引用

页码：133 / 140

页数：8

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