Challenges in Post-Silicon Validation of High-Speed I/O Links

被引：0
|
作者：
Gu, Chenjie [1 ]
机构：
[1] Intel Corp, Santa Clara, CA 95051 USA
来源：
2012 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) | 2012年
关键词：
D O I：
暂无
中图分类号：
TP31 [计算机软件];
学科分类号：
081202 ; 0835 ;
摘要：
There are increasingly number of analog/mixedsignal circuits in microprocessors and SOCs. A significant portion of mixed-signal circuits are high-speed I/O links, including serial buses such as PCIE and parallel buses such as DDR. Post-silicon validation of I/O links is hard and time-consuming, and can be critical for making a product release qualification decision. In this paper, we try to summarize key challenges in post-silicon I/O validation. We discuss potential research directions and potential solutions to improve efficiency and quality of I/O validation.
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收藏
页码：547 / 550
页数：4
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