A System-Level Post-Silicon Validation Methodology for High-Speed Serial Interfaces

被引：0

作者：

Puligundla, Sudeep ^{[1
]}

Manikandan, T. ^{[2
]}

Sunderland, Paul ^{[1
]}

Vineeth, V. L. ^{[2
]}

Daffron, Christopher ^{[3
]}

Nathal, Moises Puga ^{[3
]}

Gupta, Anshu ^{[2
]}

Tudoran, Felix ^{[1
]}

Linn, Timothy ^{[1
]}

Huang, Wayne ^{[4
]}

Luhadia, Sukay ^{[1
]}

Gardiner, Scott ^{[1
]}

Saikiran, V ^{[2
]}

机构：

[1] Intel Corp, Hillsboro, OR 97124 USA

[2] Intel Corp, Bangalore, Karnataka, India

[3] Intel Corp, Austin, TX USA

[4] Intel Corp, Taipei, Taiwan

来源：

2022 IEEE INTERNATIONAL TEST CONFERENCE INDIA (ITC INDIA) | 2022年

关键词：

High-Speed IO Testing; Post-Silicon Validation; Platform Level Test; System Test;

D O I：

10.1109/ITCINDIA202255192.2022.9854565

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

High-Speed Serial IO interfaces supporting data rates of several tens and hundreds of giga bits per second are ubiquitous in today's server and client platforms for chip-tochip and board-to-board communications. Careful system level validation of these interfaces is critical for high quality product releases and is challenging in the constraints of tight validation cycles. This paper presents a post-silicon validation methodology applicable to such interfaces that is proven to be efficient in detecting bugs, both at the silicon and system level, enabling high-quality product releases on time.

引用

页数：5

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