Post-Silicon Validation Opportunities, Challenges and Recent Advances

被引：0
|
作者：
Mitra, Subhasish [1 ,2 ]
Seshia, Sanjit A. [3 ]
Nicolici, Nicola [4 ]
机构：
[1] Stanford Univ, Dept EE, Stanford, CA 94305 USA
[2] Stanford Univ, Dept CS, Stanford, CA 94305 USA
[3] Univ Calif Berkeley, Dept EECS, Berkeley, CA USA
[4] McMaster Univ, Dept ECE, Hamilton, ON, Canada
来源：
PROCEEDINGS OF THE 47TH DESIGN AUTOMATION CONFERENCE | 2010年
基金：
加拿大自然科学与工程研究理事会; 美国国家科学基金会;
关键词：
Post-silicon validation; BUG LOCALIZATION; X-COMPACT; SELF-TEST; PROCESSORS; FAILURE;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
Post-silicon validation is used to detect and fix bugs in integrated circuits and systems after manufacture. Due to sheer design complexity, it is nearly impossible to detect and fix all bugs before manufacture. Post-silicon validation is a major challenge for future systems. Today, it is largely viewed as an art with very few systematic solutions. As a result, post-silicon validation is an emerging research topic with several exciting opportunities for major innovations in electronic design automation. In this paper, we provide an overview of the post-silicon validation problem and how it differs from traditional pre-silicon verification and manufacturing testing. We also discuss major post-silicon validation challenges and recent advances.
引用
收藏
页码：12 / 17
页数：6
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