FPGA implementation of the JPEG2000 binary arithmetic (MQ) decoder

被引：3

作者：

Lucking, David J. ^{[1
]}

Balster, Eric J. ^{[2
]}

Hill, Kerry L. ^{[1
]}

Scarpino, Frank A. ^{[1
]}

机构：

[1] AFRL, Wright Patterson AFB, OH USA

[2] Univ Dayton, Dayton, OH 45469 USA

来源：

JOURNAL OF REAL-TIME IMAGE PROCESSING | 2013年 / 8卷 / 04期

关键词：

JPEG2000 binary arithmetic decoder; MQ decoder; FPGA;

D O I：

10.1007/s11554-011-0214-9

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

A flexible FPGA implementation of the JPEG-2000 binary arithmetic decoder is presented in this paper. The proposed JPEG2000 binary arithmetic decoder reduces the amount of resources used on the FPGA allowing 19% more entropy block decoders to fit on chip and consequently increasing the throughput by 21% beyond previous designs.

引用

页码：411 / 419

页数：9

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