Design and Modeling of Monolithic Integrated Millimeterwave Chip-Package Antennas and Wireless Communication Links

被引：0
|
作者：
Russer, J. [1 ]
Mukhtar, F. [1 ]
Wane, S. [2 ]
Bajon, D. [3 ]
Russer, P. [1 ]
机构：
[1] Univ Munich, Inst Nanoelect, D-80539 Munich, Germany
[2] NXP Semiconductors, Caen, France
[3] Univ Toulouse, ISAE, Toulouse, France
来源：
2012 IEEE ASIA-PACIFIC CONFERENCE ON ANTENNAS AND PROPAGATION (APCAP) | 2012年
关键词：
Integrated millimeterwave antennas; Generalized Foster equivalent circuit; Compact model generation;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The design of a silicon monolithic integrated antenna for millimeterwave sensing and on-chip communication applications is presented. To enable an efficient co-design with monolithic integrated mixed-signal circuits on the system-on-chip level, a compact lumped element circuit model for an on-chip communication link is extracted from measurement data of the on-chip communication link. The circuit model is of generalized Foster type and accounts also for the losses. Design, measurement and modeling results are presented.
引用
收藏
页码：211 / +
页数：2
相关论文
共 50 条
  • [21] Chip-package codesign of integrated voltage-controlled oscillator in LCP substrate
    Bavisi, Amit
    Dalmia, Sidharth
    Swaminathan, Madhavan
    White, George
    Sundaram, Venky
    IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2006, 29 (03): : 390 - 402
  • [22] Chip-package co-design of power distribution network for system-in-package applications
    Kim, GW
    Kam, DG
    Chung, DH
    Kim, JH
    6TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, PROCEEDINGS (EPTC 2004), 2004, : 499 - 501
  • [23] Wireless Chip-to-Chip Communication in Three-Dimensional Integrated Circuits Using Microbump Antennas
    Loke, Wing-Fai
    Lu, Julia Hsin-Lin
    Peroulis, Dimitrios
    Jung, Byunghoo
    2013 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST (IMS), 2013,
  • [24] On-chip wireless interconnection with integrated antennas
    Kim, K
    Yoon, H
    O, KK
    INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, : 485 - 488
  • [25] Upper/Lower boundary estimation of package interconnect parasitics for chip-package co-design
    Song, Eunseok
    Lee, Heeseok
    Leet, Jungtae
    Jin, Woojin
    Choi, Kiwon
    Yang, Sa-Yoon
    ISQED 2007: PROCEEDINGS OF THE EIGHTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2007, : 573 - +
  • [26] Noise isolation modeling and experimental validation of power distribution network in chip-package
    Park, Hyunjeong
    Yoon, Changwook
    Koo, Kyoungchoul
    Kim, Joungho
    2007 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY: WORKSHOP AND TUTORIAL NOTES, VOLS 1-3, 2007, : 270 - 275
  • [27] Chip-package co-design for high performance and reliability off-chip communications
    Shen, M
    Liu, J
    Zheng, LR
    Tenhunen, H
    PROCEEDINGS OF THE SIXTH IEEE CPMT CONFERENCE ON HIGH DENSITY MICROSYSTEM DESIGN AND PACKAGING AND COMPONENT FAILURE ANALYSIS (HDP'04), 2004, : 31 - 36
  • [28] Integrated chip-size antennas for wireless microsystems: Fabrication and design considerations
    Mendes, PM
    Polyakov, A
    Bartek, M
    Burghartz, JN
    Correia, JH
    SENSORS AND ACTUATORS A-PHYSICAL, 2006, 125 (02) : 217 - 222
  • [29] Employing EBG in Wireless Inter-chip Communication Links: Design and Performance
    Al-Alem, Yazan
    Kishk, Ahmed A.
    Shubair, Raed M.
    2020 IEEE INTERNATIONAL SYMPOSIUM ON ANTENNAS AND PROPAGATION AND NORTH AMERICAN RADIO SCIENCE MEETING, 2020, : 1303 - 1304
  • [30] An integrated system for setting the optimal parameters in IC chip-package wire bonding processes
    Hou, Tung-Hsu
    Chen, Shyh-Huei
    Lin, Tzu-Yu
    Huang, Kun-Ming
    International Journal of Advanced Manufacturing Technology, 2006, 30 (3-4): : 247 - 253
12345