Design and Modeling of Monolithic Integrated Millimeterwave Chip-Package Antennas and Wireless Communication Links

被引：0
|
作者：
Russer, J. [1 ]
Mukhtar, F. [1 ]
Wane, S. [2 ]
Bajon, D. [3 ]
Russer, P. [1 ]
机构：
[1] Univ Munich, Inst Nanoelect, D-80539 Munich, Germany
[2] NXP Semiconductors, Caen, France
[3] Univ Toulouse, ISAE, Toulouse, France
来源：
2012 IEEE ASIA-PACIFIC CONFERENCE ON ANTENNAS AND PROPAGATION (APCAP) | 2012年
关键词：
Integrated millimeterwave antennas; Generalized Foster equivalent circuit; Compact model generation;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The design of a silicon monolithic integrated antenna for millimeterwave sensing and on-chip communication applications is presented. To enable an efficient co-design with monolithic integrated mixed-signal circuits on the system-on-chip level, a compact lumped element circuit model for an on-chip communication link is extracted from measurement data of the on-chip communication link. The circuit model is of generalized Foster type and accounts also for the losses. Design, measurement and modeling results are presented.
引用
收藏
页码：211 / +
页数：2
相关论文
共 50 条
  • [41] WEARABLE ANTENNAS DESIGN FOR WIRELESS COMMUNICATION
    Schilingovski, Pavel
    Vulfin, Vladimir
    Sayfan-Altman, Shai
    Shavit, Reuven
    2017 IEEE INTERNATIONAL CONFERENCE ON MICROWAVES, ANTENNAS, COMMUNICATIONS AND ELECTRONIC SYSTEMS (COMCAS), 2017, : 585 - 587
  • [42] Chip-package and antenna co-design of a tunable UWB transmitter in System-on-Package with on-chip versus off-chip passives
    Nejad, Majid Baghaei
    Tenhunen, Hannu
    Zheng, Li-Rong
    ESTC 2006: 1ST ELECTRONICS SYSTEMINTEGRATION TECHNOLOGY CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2006, : 291 - +
  • [43] Chip-Package Co-Design for Suppressing Parallel Resonance and Power Supply Noise
    Mido, Tatsuya
    Kobayashi, Ryota
    Kubo, Genki
    Otsuka, Hiroki
    Kobayashi, Yoshinori
    Fujii, Hideyuki
    Sudo, Toshio
    2012 IEEE 21ST CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, 2012, : 347 - 350
  • [44] RF robustness enhancement through statistical analysis of chip-package co-design
    Duo, XZ
    Zheng, LR
    Tenhunen, H
    2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS, 2004, : 988 - 991
  • [45] Concurrent chip-package design for 10GHz global clock distribution network
    Shen, MG
    Zheng, LR
    Tjukanoff, E
    Isoaho, J
    Tenhunen, H
    55th Electronic Components & Technology Conference, Vols 1 and 2, 2005 Proceedings, 2005, : 1554 - 1559
  • [46] Constraint driven I/O planning and placement for chip-package co-design
    Xiong, Jinjun
    Wong, Yiu-Chung
    Sarto, Egino
    He, Lei
    ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 2006, : 207 - 212
  • [47] Compact Shorted Stacked-Patch Antenna Integrated with Chip-Package Based on LTCC Technology
    Li, Yongjiu
    Li, Long
    Dai, Xiwang
    Zhu, Cheng
    Huo, Feifei
    Dong, Gang
    INTERNATIONAL JOURNAL OF ANTENNAS AND PROPAGATION, 2014, 2014
  • [48] Potentials of chip-package co-design for high-speed digital applications
    Tröster, G
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS, 1999, : 423 - 424
  • [49] Electromagnetic modeling and analysis of wireless communication antennas
    Hoorfar, A
    Jamnejad, V
    IEEE MICROWAVE MAGAZINE, 2003, 4 (01) : 51 - 67
  • [50] Design considerations for millimeter wave antennas within a chip package
    Liu, D.
    Gaucher, B.
    2007 INTERNATIONAL WORKSHOP ON ANTI-COUNTERFEITING, SECURITY, AND IDENTIFICATION, 2007, : 13 - +
12345