共 50 条
- [1] New hardware-efficient algorithm and architecture for the computation of 2-D DCT on a linear systolic array ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings, 1999, 6 : 3517 - 3520
- [2] New hardware-efficient algorithm and architecture for the computation of 2-D DCT on a linear systolic array ICASSP '99: 1999 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, PROCEEDINGS VOLS I-VI, 1999, : 3517 - 3520
- [4] Hardware-efficient steering matrix computation architecture for MIMO communication systems PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 304 - 307
- [5] A new hardware-efficient architecture for programmable FIR filters IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1996, 43 (09): : 637 - 644
- [9] A Hardware-Efficient Algorithm for Real-Time Computation of Zadoff–Chu Sequences Journal of Signal Processing Systems, 2013, 70 : 209 - 218
- [10] An Internal Folded Hardware-Efficient Architecture for Lifting-Based Multi-Level 2-D 9/7 DWT APPLIED SCIENCES-BASEL, 2019, 9 (21):