Signal probability for reliability evaluation of logic circuits

As integrated circuits scale down into nanonieter dimensions, a great reduction an the reliability of combinational blocks is expected. This way, the susceptibility of circuits to intermittent and transient faults is becoming a key parameter in the evaluation of logic circuits, and fast and accurate ways of reliability analysis must be developed. This paper presents a reliability analysis methodology based on signal probability, which is of straightforward application and can be easily integrated in the design flow. The proposed methodology computes circuit's signal reliability as a function of its logical masking capabilities, concerning multiple Simultaneous faults Occurrence. (C) 2008 Elsevier Ltd. All rights reserved.