Signal probability for reliability evaluation of logic circuits

被引：61

作者：

Franco, Denis Teixeira ^{[1
,2
]}

Vasconcelos, Mai Correia ^{[1
]}

Naviner, Lirida ^{[1
]}

Naviner, Jean-Francois ^{[1
]}

机构：

[1] Telecom ParisTech, LTCI CNRS, Inst TELECOM, COMELEC Dept, F-75013 Paris, France

[2] Fundacao Univ Fed Rio Grande, Fdn Univ Fed Rio Grande, Rio Grande, RS, Brazil

来源：

MICROELECTRONICS RELIABILITY | 2008年 / 48卷 / 8-9期

关键词：

D O I：

10.1016/j.microrel.2008.07.002

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

As integrated circuits scale down into nanonieter dimensions, a great reduction an the reliability of combinational blocks is expected. This way, the susceptibility of circuits to intermittent and transient faults is becoming a key parameter in the evaluation of logic circuits, and fast and accurate ways of reliability analysis must be developed. This paper presents a reliability analysis methodology based on signal probability, which is of straightforward application and can be easily integrated in the design flow. The proposed methodology computes circuit's signal reliability as a function of its logical masking capabilities, concerning multiple Simultaneous faults Occurrence. (C) 2008 Elsevier Ltd. All rights reserved.

引用

页码：1586 / 1591

页数：6

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