A cost-effective CORDIC-based architecture for adaptive lattice filters

被引:0
|
作者
Shiraishi, S [1 ]
Haseyama, M [1 ]
Kitajima, H [1 ]
机构
[1] Hokkaido Univ, Grad Sch Engn, Sapporo, Hokkaido 0608628, Japan
关键词
adaptive filter; gradient adaptive lattice; CORDIC; VLSI architecture;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents a cost-effective CORDIC-based architecture for adaptive lattice filters. An implementation method for an ARMA lattice filter using the CORDIC algorithm has been proposed. The previously proposed method can provide a simple filter architecture; however, it has problems such as redundant structure and numerical inaccuracy. Therefore, by solving each problem we derive a new non-redundant filter architecture with improved numerical accuracy. The obtained filter architecture provides a low cost ARMA lattice filter in which high-precision data processing is feasible. In addition, the proposed architecture can be applied to AR-type lattice filters, so that it may have several applications in adaptive signal processing. The presented filter architecture is useful from a hardware point of view because it facilitates an effective VLSI design of various adaptive lattice filters.
引用
下载
收藏
页码:567 / 576
页数:10
相关论文
共 50 条
  • [41] A Novel Paradigm of CORDIC-Based FFT Architecture Framed on the Optimality of High-Radix Computation
    Ayan Banerjee
    Anindya Sundar Dhar
    Circuits, Systems, and Signal Processing, 2021, 40 : 311 - 334
  • [42] A Novel Paradigm of CORDIC-Based FFT Architecture Framed on the Optimality of High-Radix Computation
    Banerjee, Ayan
    Dhar, Anindya Sundar
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2021, 40 (01) : 311 - 334
  • [43] CORDIC-based direct digital frequency synthesizer: Comparison with a ROM-based architecture in FPGA implementation
    Park, M
    Kim, K
    Lee, JA
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2000, E83A (06) : 1282 - 1285
  • [44] CORDIC-based unified VLSI architecture for implementing window functions for real time spectral analysis
    Ray, K. C.
    Dhar, A. S.
    IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2006, 153 (06): : 539 - 544
  • [45] A Cost-effective Interconnect Architecture for Interconnection Network
    Wang, Xinyu
    Xiang, Dong
    Yu, Zhigang
    IETE JOURNAL OF RESEARCH, 2013, 59 (02) : 109 - 117
  • [46] DynaShield: A Cost-Effective DDoS Defense Architecture
    Zheng, Shengbao
    Yang, Xiaowei
    SIGCOMM'18: PROCEEDINGS OF THE ACM SIGCOMM 2018 CONFERENCE: POSTERS AND DEMOS, 2018, : 15 - 17
  • [47] An effective architecture of the pipelined LMS adaptive filters
    Kimijima, T
    Nishikawa, K
    Kiya, H
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1999, E82A (08): : 1428 - 1434
  • [48] A cost-effective parallel architecture for the CodeRAKE receiver
    Youssef, Mazen
    Monteiro, Fabrice
    Dandacbe, Abbas
    Diou, Camille
    2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4, 2007, : 447 - 450
  • [49] The VADA Architecture for Cost-Effective Data Wrangling
    Konstantinou, Nikolaos
    Koehler, Martin
    Abel, Edward
    Civili, Cristina
    Neumayr, Bernd
    Sallinger, Emanuel
    Fernandes, Alvaro A. A.
    Gottlob, Georg
    Keane, John A.
    Libkin, Leonid
    Paton, Norman W.
    SIGMOD'17: PROCEEDINGS OF THE 2017 ACM INTERNATIONAL CONFERENCE ON MANAGEMENT OF DATA, 2017, : 1599 - 1602
  • [50] Cost-effective Resilient FPGA-based LDPC Decoder Architecture
    de Souza, Eduardo N.
    Nazar, Gabriel L.
    2019 IEEE 25TH INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS 2019), 2019, : 84 - 89