A Multi-mode 30 GHz 2 Degree RMS Power Efficient Phase-Locked Loop Frequency Synthesizer

被引:0
|
作者
Mahalingam, Nagarajan [1 ]
Wang, Yisheng [2 ]
Thangarasu, Bharatha Kumar [2 ]
Ma, Kaixue [3 ]
Yeol, Kiat Seng [1 ,2 ]
Tan, Yung Sern [1 ]
机构
[1] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore, Singapore
[2] Singapore Univ Technol & Design, Engn Prod Dev, Singapore, Singapore
[3] Univ Elect Sci & Technol China, Sch Phys Elect, Chengdu, Peoples R China
关键词
30; GHz; 60; fractional-N; frequency synthesizer; multi-mode; PLL; VCO;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a multi-mode power efficient PLL synthesizer with low power consumption and low phase noise using coupled-tank voltage controlled oscillator and local oscillator chain for 60 GHz transceiver supporting IEEE 802.11 ad standards. Fabricated in commercial 0.18 mu m SiGe BiCMOS process with a single 1.8 V supply, the PLL synthesizer covers frequency from 29.5 GHz to 33.5 GHz with a RMS noise of 2 degrees integrated over phase noise from 10 kHz to 10 MHz. The fully integrated PLL synthesizer consumes low power of only 63 mW and occupies an area of 1.1 mm x 1.6 mm excluding the loop filter.
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页数:4
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