On the Optimization of SBST Test Program Compaction

Due to the increasing adoption of SBST solutions for both the end-of-manufacturing and the in-field test of SoC devices, the need for effective techniques able to reduce the duration of existing test programs became more pressing. Previous works demonstrated that this task is highly computational intensive and it is beneficial to partition it, e.g., by addressing the test program for one hardware module at a time. However, existing compaction techniques may become completely ineffective when dealing with faults which relate to memory addresses. This paper clarifies this issue and proposes possible solutions. Their effectiveness is experimentally demonstrated on a OR1200 pipelined processor.