A bit-line GND sense technique for low-voltage operation FeRAM

被引：3

作者：

Kawashima, S ^{[1
]}

Endo, T ^{[1
]}

Yamamoto, A ^{[1
]}

Nakabayashi, K ^{[1
]}

Nakazawa, M ^{[1
]}

Morita, K ^{[1
]}

Aoki, M ^{[1
]}

机构：

[1] Fujitsu Labs Ltd, Atsugi, Kanagawa 2430197, Japan

来源：

2001 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2001年

关键词：

D O I：

10.1109/VLSIC.2001.934216

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We propose a sense scheme that a pMOS charge-transfer maintains bit-line level near the GND level when the plate line goes high. The scheme supplies 0.5 V higher read-out voltages across the cell capacitors and achieves a 0.4 V higher differential amplitude in a 512-cell per bit-line structure than conventional DRAM sense scheme, A Shifted bias Plate Line layout enables a minimum number of bit-lines to be activated and achieves 8.06 mW @ 3 V, 5 MHz, about same power as conventional device.

引用

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页码：127 / 128

页数：2

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